CadEnhance defines 2 different flows (Physical and Logical) for FPGA and CPLD symbol creation.
Figure 6 below shows the I/O structure of a typical modern FPGA/CPLD which is built as a collection of general purpose I/O banks and specialty HIGH speed I/O banks. Each I/O bank usually contains a collection of pins which can be used as inputs, outputs or input/output. Generally each bank also contains a set of voltage pins and special purpose pins that allow the banks to inter-operate with different IO standards.

See the FPGA Pin-Data Files Page for Information on how the Pin Data is provided to PartBuilder in these 2 flows.

The FPGA PHYSICAL FLOW

The Physical flow is the typical flow used by most librarians where the symbols for an FPGA are broken up into this collection of I/O banks and power bodies using the generic physical names assigned by the vendor for each pin. Figure 7 below, shows 2 typical symbols that might be generated for 2 of the FPGA I/O Banks. The partBuilder tool shines in this application since the regular structure of the IO pins are typically very easy to split into multiple symbols. The symbols for an FPGA with 2000 pins can be defined almost as quickly as one with 100 pins, and the symbolOrder files that work for one part need only slight updates to work for another part.
When an FPGA symbol is created in the Physical flow, it is up to the schematic designer to connect wires to the proper pins using the final pin report of the actual design.

Figure 6: Modern FPGA/CPLD I/O BANK structures

Figure 7:Typical FPGA SYMBOLS from PHYSICAL FLOW

The FPGA LOGICAL Flow

Instead of drawing the symbols for the FPGA as a collection of I/O banks, The Logical flow is used to draw the FPGA as a series of symbols that show the intended use of the pins in the actual design. All of the Pins that have been programmed are given the names found in the design, while spare and power pins are given the generic physical names from the vendor. The Logical Flow provides much more flexibility to the designer, and greatly enhances the ability to correctly connect the FPGA in the design. Figure 8 Below shows part of an FPGA symbol built using the logical flow where the pin names are given names explicit to the design, so it is easy to check connectivity. Each symbol can contain multiple banks worth of pins.

Figure 8: Typical FPGA symbols From Logical Flow

The FPGA Logical flow requires 2 pin information files as input, the Physical package File and the LOGICAL Pin Report File. PartBuilder reads the 2 files, builds the logical pin names from the PAD File and the Physical pin_names from the package File. If a pin is used in the application, it gets assigned the name from the LOGICAL Pin Report File. Otherwise the pin gets assigned the name from the PHYSICAL pacakge file so that the user can precisely control the placement via the bank pin name.

When the Logical FLOW is used, the task of connecting the FPGA in the design becomes much simpler and less prone to change. First of all the designer does not have to lookup the pin_number of a pin in the compiled fpga pin report to find its function since the pin already exists in the symbol with the logical name. Second, the Logical division of the symbols does not tend to change too much from start to finish, while the pin numbers assigned to the logical functions may change multiple times in the design cycle to optimize timing and functionality. If the pin numbers do change, The designer can re-run partBuilder with the new compiled pin report which will re-create the symbols with the same pin-names but with the new pin-numbers. To update the schematic, the designer only has to replace the symbols with the newly generated symbols. There will be no need to go through and re-wire the FPGA symbols since the pin names didn't change.