The PinWire GUI.

After double clicking the Pin_Wire tool from the HDL Tool Selection Tree, the PinWire GUI will popup, similar to the one shown on the right.

The GUI has 5 main sections:

Signal/Pin and Power Rename Rules
Signal Naming Options
Part Options
Execute and Settings Buttons
Status Window

Signal/Pin and Power Rename Rules

Please refer to PinWire Config Files section for important concepts when working with the COMP_CFG_FILE.

Working Component Buttons
1. Select Button
  1. When the user presses the select button, they will be prompted to select a component in the schematic that they want to load/store settings for.
  2. PinWire builds a config file name to load from (and to store to) based on the schematic block_name and the component name. If the config file exists, PinWire will update its settings from that file.
  3. C:/Allegro/design/CE_SCHEMATICS/16_6/fpga_logical_vs_physical/REV_00X/007_REV_1/CE_HDL/PIN_WIRE/xil_physical_fpga_XCVU3P_FFVC1517_ctl.txt
2. Save Config Button
  1. All current settings will be stored to the currently selected COMP_CFG_FILE
File Selections
1. COMP_CFG_FILE
  1. Select a configuration file to store all the File Selections in for the current component
  2. PinWire automatically names this file the first time you select a working component
    1. it concatenates the block_name and the component_name together and stores the file in the default CE_HDL/PIN_WIRE directory location.
2. FPGA_PIN_REPORT
  1. If the device is an FPGA (from Xilinx, Altera, Lattice and/or Microsemi) the user can provide the FPGA_PIN_REPORT file from the vendor. This will be the primary source of SIG_NAMES for each ASSIGNED FPGA pin. (No wires are added to pins that are unassigned in the FPGA_PIN_REPORT file)
3. SIG_RENAME_RULES
  1. The SIG_RENAME_RULES entry is interesting, because it can either specify a comma separated set of MATCH:REPLACE rules or a file containing a set of RENAME_RULES.
    1. Rather than repeat all the information about SIG_RENAME_RULES here, refer to this link describing SIG_RENAME_RULES from the PartBuilder documentation
4. PWR_RAIL_RENAMES
  1. This is the file that is used to store the power pin to net name mapping rules.
  2. When the user selects Edit, they will be presented with another GUI, allowing them to control the how Pins with names matching the RAIL_MATCH column are assigned SCH_NET_NAMES
  3. For each group of power pins, the user can enter the voltage specified in the datasheet for the part, and the block level net_name that should be connected to that group of pins.
  4. If an FPGA device is selected and PinWire knows how extract voltage data for the power pins from the configured FPGA_PIN_REPORT file, the voltages for each group of power pins will be set as a starting point for the user
  5. When PinWire is used to connect wires to the power pins, it will look to see if the file specified in the PWR_RAIL_RENAMES selection exists and if it has a remapped name for the power pin. If so, it will use the assigned netName from that

Signal Naming Options

This section of the GUI controls how the final SIG_NAME for each pins wire will be created. See How PinWire chooses the SIG_NAME to add to each pins wire for the details

Signal Name [ or Prefix ]
1. Use 'Signal Name' Entry as SIG_NAME
2. Use PIN_NAME as SIG_NAME
3. Lookup PIN_NAME in FPGA_REPORT
4. Use PIN_VALUE in SIG_NAME
Signal name suffix
1. If the user fills in this entry, the contenets will be appended as a suffix to the configuration
2. PinWire will prompt the user to lead this suffix with an underscore if one is not entered
Move Bus Digits To End
Vectorize PIN_NAMEs ending in Numbers
Skip Power Pins
Strip Power Pin Suffixes

Execute and Settings Buttons

Watch This short video for a quick demonstration on how to define the wires you want in PinWire: [ DefiningWiresWithPinWire ]

Run
- The Run button starts the process of adding wires.
- The user is prompted inside the schematic tool to create a box around the symbol pins in AllegroHDL and then to set an endpoint where the wires will terminate.
- The wires and selected components are added to the schematic and then AllegroHDL returns done status to the CE_HDL tool which waits for the operation to complete
  - There is a slight chance of a hangup in this step if the user does not follow the prompts properly in the AllegroHDL tool. Watch the video in the link above to learn more
  - It is important that the user click once (and let go) to start a box to surround the pins they want to add wires to,
  - The 2nd click will complete the box that is drawn around the pins.
  - The third click is used to establish the endpoint of the wires that will be added
    - The third click also establishes the direction for the wires and should provide enough room to add the signal_names.
Redo
- The Redo button is equivalent to pressing Undo and then Run.
- It undoes the last set of connections that were added and then prompts the user like the Run Button
Undo
- Undo deletes the wires and parts that were last added by a successful run operation.
View Settings
- This will popup the config menu
Save Settings
Help
Done
- Pressing the Done button closes the PinWire Gui (which can then be relaunched if necessary using the CE_HDL GUI)

Part Options

Status Window

This window shows the progress of the startup and communication between CE-HDL and AllegroHDL
Filenames and directories are shown as blue underlined hyperlinks that the user can double-click to open a file or ctrl-click to open a file-browser starting in the directory where the file lives
There are 3 main message types in the status window STAT, DBG and WARN
1. STAT messages provide progress information from at a high level.
2. DBG messages provide highly detailed information and by default, they are not displayed in the status window, but they can be enabled with the DBG check box.
3. WARN messages are printed in red bold font and typically show abnormal status.
The Status Window can be cleared using the Clear Status Button
The open Status File button can be used to see all the DBG, STAT and WARN messages in a text editor for easy searching

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