Are you Using Hierarchical Designs?

I find it incredible that in 2019, one year out from 2020, most Allegro Design Entry HDL customers seem to avoid Hierarchical Schematic Design (HSD) like the plague. The next tier of customers are starting to test HSD in their workflows.

The companies I have worked for have been reaping the benefits of HSD since early 2000 when it was still known as Concept (before Concept-HDL, Allegro-HDL, or Design Entry HDL). I think we started with version 12.5.

For us, HSD was a necessity, not a luxury, and the seeds of some cadEnhance tools were planted to help simplify HSD and work around the problems that occurred when you weren't careful.

Creating the HSD

When creating an Allegro HDL Hierarchical Schematic, it is worth spending a fair amount of time planning the initial Hierarchical Structure. The design consists of a Top Level where common circuitry and a mix of Hierarchical Blocks (HBLOCKS) can be placed. Each HBLOCK design may instantiate even more levels of Hierarchy. When partitioned properly, the design is easy to work with and modify and allows easy substitution of key blocks. A good HSD lends itself well to reuse in other designs, saving countless days of development. It is important to understand the the initial plan may not be what you end up with, but a good starting plan should be easy to morph into the final structure.

Planning the Hierarchy

It is important to keep several goals in mind when you plan your Hierarchy

Efficiency of Creation
1. Many first time Hierarchical designers go a little overboard and create too many hierarchical blocks (HBLOCKS) to try and solve the problem. They create one HBLOCK for every IC, and another HBLOCK for every function. This becomes difficult to manage because a symbol mus be maintained for each block in the design, and connectivity changes can cause a nightmare ripple effect.
2. Since version 16.6 Cadence has created the concept of NET_GROUPS which let you bundle multiple disparate signalNames into one port which helps with connectivity issues. design harder to follow and verify.
3. With good forethought, the number of HBLOCKS can be kept to a minimum so that design changes are easier to manage
Reuse
1. If your Hierarchy is designed efficiently, the major blocks will lend themselves to reuse in multiple designs either in their exact form or with simple modifications. This can shave huge amounts of development time when creating a new design from an existing design (or pieces of multiple existing designs).
2. A well planned design lends itself to packaging using Allegro SUB_DESIGNS. Here the cadEnhance pkgAssitant tool can be used to incrementally package groups of blocks for the design. It provides a a smoother design process. With SUB_DESIGNS the base reference designators are identical between blocks and get uniquified with some levels of suffixing) . The use of Sub-designs also keeps some of the known gremlins that can appear when the Allegro packager compiles the full complex hierarchical design at bay.
Substitution
1. An Intelligent Hierarchical Design will allow the user to substitute out Key functions by simply swapping an HBLOCK.
  1. This can provide incredible time savings if you have to swap FPGA devices, families or vendors.
    1. An FPGA block with its power HBLOCK inside the block can be helpful here since the port names may not change, but the required power may be completely different. If we feed 12V and 3.3V and a set of enable signals into the FPGA HBLOCK, and have the power HBLOCK provide the more granular rails to the FPGA. The changes required at the high level block interfaces will be minimized.
  2. The same applies to a design with a micro-controller, switch or other networking function. If you want to migrate to a newer more powerful or lower power device, a well designed HBLOCK will lend itself to easy substitution.
Don't be afraid of multiple levels, but don't go crazy with levels either.
1. multiple HBLOCK levels will allow you to copy and reuse placements and routing at the PCB level.
2. Lets say you have an FPGA with 2 memory interfaces (either to a DIMM or discrete memory), it often makes sense to instantiate the 2 DIMMS at the same level in the FPGA block to avoid having to route the DIMM signals out of the FPGA block and into a DIMM block. If the memory interface consists of multiple devices, it would makes sense to create an HBLOCK to contain the multiple memory devices and then instantiate the memory interface HBLOCK twice inside the FPGA Block.
3. The HBLOCK will help the packager keep the proper components together.

Using CadEnhance Tools in your HSD project

Once the Structure is in place, the CadEnhance PartBuilder, CE-HDL tools CE_HDL and PartBuilder work best if you create the design from the bottom up.

The reccomended flow is to work in your top level design. For simplicity sake, we always name the top block:"top". On any page you want a top level block, place empty placeholders for blocks using the block→add command

Starting in the low level HBLOCKS, CE-HDL can be used to create wire names derived from the pinNames of the devices instantiated in those blocks. Any wire that gets connected to an io-port symbol will create a Port for the HBLOCK. Once the wires are created, PartBuilder can be run to create the symbol for the HBLOCK where the automatically named wire names are used to create port names on the HBLOCK. CE-HDL is then used to wire the HBLOCK symbol, where the connection names are created from the HBLOCK port-names, using simple prefixes or more complex rename rules to create unique names. In this way, the majority of the design connections are created using strong naming conventions where signal names can be traced back to the initiating pinNames. This provides great accuracy in the net-naming and lends itself well to automated checking.

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Allegro-HDL Hierarchical Schematic Design (HSD) from the Bottom Up

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