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The BUILD_ECS MACRO Creates a Named ELECTRICAL_CONSTRAINT_SET (ECS) which can be applied to matching NetNames 

Electrical Constraint Sets

An Electrical Constraint Set (ECS) is use to constrain the Electrical attributes of Nets 

BUILD_ECS can specify many different constraints to apply to a group of signals, and can also apply a PHYSICAL_CONSTRANT_SET (PCS) to the same group.

PARAMETERS that can be constrained include:

VIAS_MAX,VIAS_MATCH,MIN_PROP_DLY,MAX_PROP_DLY,MIN_TOTAL_ETCH,MAX_TOTAL_ETCH,

TOP_MAP_MODE,TOP_VERIFY_SCHEDULE,TOP_SCHEDULE_CONTROL,STUB_LENGTH,MAX_EXPOSED,MAX_PARALLEL,LAYER_SETS



BUILD_ECS  

This Line tells dal constraints to create a new named ECS

Syntax: 

BUILD_ECS  | NAME=> | NAME_FOR_ECS


TYPE

The TYPE Attribute  tells dal constraints what type of ECS the user wants to create

Valid options:

DIFF_PAIR and SINGLE_ENDED

Syntax:

TYPE=>[DIFF_PAIR|SINGLE_ENDED]

The SINGLE_ENDED ECS allows the user to define multiple sets of properties to apply to a group of single ended signals.

The DIFF_PAIR ECS can be used to add the same parameters as the SINGLE_ENDED, and can be used to add the DIFF_PAIR ECS Properties/Attributes listed below


SINGLE_ENDED Properties/Attributes supported by Allegro Constraint System

If Bold they are also supported by dal constraint

  1. VIAS_MAX
  2. VIAS_MATCH
  3. MIN_PROP_DLY
  4. MAX_PROP_DLY,
  5. MIN_TOTAL_ETCH
  6. MAX_TOTAL_ETCH
  7. TOP_MAP_MODE
  8. TOP_VERIFY_SCHEDULE
  9. TOP_SCHEDULE_CONTROL
  10. STUB_LENGTH
  11. MAX_EXPOSED
  12. MAX_PARALLEL
  13. LAYER_SETS


DIFF_PAIR ECS Properties/Attributes

The Dynamic Diff Pair constraints are used to track and flag the intra-pair skew from the signal source to its destination.

Differential pair routing only works well when the signal edges or transitions are closely aligned as they travel from one end to the other.  As speeds increase, the edge times get smaller and smaller and the margin for error becomes greater. When a diff pair route turns a corner, the outside pair wire takes a longer path than the inside pair wire causing unwanted skew between the signals. If this skew is significant, the edge transitions start to get out of phase and the differential pair loses some of its magical properties.  In this case the skew needs to be removed as quickly as it can be.  This can be accomplished by making sure the next turn goes the opposite direction so that the inside wire is now the outside wire.  Another method is to add  a small 'bump' to the inside wire whose length match the extra length that the outside wire experienced. The bump should be added as close as possible to the corner turn so that the signal transitions travel the majority of the diff_pair length in match step.

The Cadence Allegro Constraint System provides a handful of diff_pair tolerance properties to enable tracking of the skew from the transmitter output to the receiver input.

Properties are:

  1. GATHER_CONTROL
  2. MAX_UNCOUPLED
  3. DPA_TOLERANCE 
  4. DPA_MAX_LEN
  5. STATIC_PHASE

In the sample CRF worksheet a DIFF_PAIR_CALC_WORKSHEET page is provided to help calculate rational values for these parameters that are used to constrain the DIFF_PAIRS, based on the Bit Rate of the actual DiffPair. It can be very beneficial to use a reference to the cells that hold the values calculated on the WORKSHEET to set the value for the properties instead of hard-coding the values. If you use a reference to a cell that holds a calculation, and update something in the the Calculation worksheet, then the property values will automatically be updated.

AUTO_IDENTIFY_PIN_DIR MACRO with Dynamic DiffPair

The Dynamic Phase constraints always start at the driver pin and end at the receiver pin so its important that the pinTypes are correctly defined in the netlist. PinType information is extracted from the schematic symbol when the netlist is created and some organizations do not pay close attention to the types when they create their symbols (some may define every pin as an inout). The AUTO_IDENTIFY_PIN_DIR MACRO in the CRF allows the user to override the pinTypes in the netlist to ensure the Dynamic Phase constraints are properly applied. 

dalTools diffpair utility

The dalTools diffpair utility provides a very helpful video on how to route diffPairs which have been constrained using the Dynamic Phase Constraints. The video is available on the 'Dyn phase' tab

ASSIGN_PCS

The ASSIGN_PCS Attribute assigns an existing  named PCS to any nets that are assigned to this ECS. This  provides a powerful way to define the controlled Impedance and or line widths for a whole group of nets.

The PCS may have been created using the BUILD_PCS MACRO or when dal constraints imported the stackup. 

Syntax: 

ASSIGN_PCS=>PCS_NAME

Example:

ASSIGN_PCS=>90_OHM_DIFF

MEMBERS

The MEMBERS=> Attribute tells dal constraints what nets to apply the new ECS to. 

Syntax:

MEMBERS=>net_match1,net_match2.... net_matchN

Example:

MEMBERS=>VCC,VDD

This tells dal constraints to assign this ECS to any net containing 'P48V' or 'P48V_RTN'

in this case the net_match is a simple text pattern 

The MEMBERS net_matches are treated as regular expressions by dal constraints and are quite powerful.

To see more information on regular expression entry see  Regular Expressions In CadEnhance Tools

NOT_MATCHING

the NOT_MATCHING Attribute is optional and works together with the MEMBERS attribute to fully define the set of target nets

Syntax:

NOT_MATCHING is a  comma separated list of patterns that will be used to exclude nets from the set of nets that match the MEMBER patterns

Example:

NOT_MATCHING=>_GOOD,_MON,_SENSE

MEMBERS and NOT_MATCHING 

Together the MEMBERS and NOT_MATCHING attributes make it very efficient to target a large set of diverse nets without having to create a very long list of specific matches. You can create a very general set of matches with the MEMBERS attribute and then exclude certain pattern matches with the NOT_MATCHING patterns.

In the above example, with MEBERS set to VCC,VDD and NOT_MATCHING set to _GOOD, _MON and _SENSE,

any netName containing  VCC or VDD would be targeted unless they contained _GOOD, _MON or _SENSE

so VCC1P8,VDD3P3_PWR, PVDD_12V, P1R5VDD would be included but VCC1P8_GOOD, PVDD_12V_SENSE and P1R5VDD_MON would not 


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