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The CadEnhance Symbol Description Language (SDL) Enables the Librarian or Engineer to Describe the Layout of pins and symbols from a very high level. It supports looping constructs and pin-name pattern matching which enables features designers haven't seen before in symbol creation tools. For example using one 45 line SDL file, you can create the symbol files for ANY FPGA in the Xilinx Virtex7 part family (some with over 2000 pins), and similar SDL files will provide support for Altera(Intel) and Lattice part families. While very powerful, the SDL is also very intuitive and simple to create.

Here we will cover the syntax and structure of the SDL, but in order to remove the intimidation factor, we will first show a simple Example

A Simple Example SDL File describing a useless FAKE_DRAM Part

The PIN_REPORT_FILE for these symbols was the SIMPLE_BGA format and contained the PINS shown to the right

The SDL was created in Excel and saved off as a .csv file For partBuilder to read

Any line starting with a '#' is a comment and is ignored by the SDL reader.

The contents of the SDL file shown on the Left guides left guides partBuilder to Create create the Symbols shown on the Right.symbols shown below

It is a mix of Symbol_Name_Definitions, Match_Statements and Pin_Spacer commands.

A Match_Statement contains a locator, optional modifiers and a pin_match defintion

DRAM_ACTL_PINS= on line 5 on row 3 is the first Symbol Name Definition and starts tells partBuilder to create a new Symbol named DRAM_ACTL_PINS containing the pins that match all the Match_Statements

The DRAM_PINS symbol ends with the ';' on line 1713

The 2nc Symbol Declaration DRAM_DQ_PINS starts at row 15 and ends at row 26

The 2nd 3rd Symbol Declaration POWER= starts on line 22 and ends at line 25

The 3rd 4th Symbol Declaration GROUND= starts on line 29 at row 33 and ends at line 31row 35

The 3rd GROUND Symbol Declaration actually creates 2 symbols GROUND and GROUND_1 because while partBuilder is adding the GND pins to both sides,

it sees that the number of pins on the symbol exceeds the ControlSetting:SYMBOL_PIN_LIMIT which was set to 75 in this case and knows it has to start =76 which so it creates a new symbol on the fly to honor that setting.

Code Block

language	perl
title	Example SDL File
linenumbers	true

#SDL FOR FAKE DRAM PART #start symbol named DRAM_PINS DRAM_PINS= left=>clk_p left=>clk_n !BALANCE_SYMBOL_SIDES+2 PSG_dq_w0:left=>dq[7:0] left=>spacer[1:0] clock:left=>dqs0 bubble:left=>enb_n0 PSG_dq_w1:right=>dq[15:8] right=>spacer[1:0] clock:right=>dqs1 bubble:right=>enb_n1 ; #end symbol named DRAM_PINS #start symbol named POWER POWER= LEFT=>VCCD RIGHT=>VCC ; #end symbol named POWER #start symbol named GROUND GROUND= BOTH=>GND ; #end symbol named GROUND

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