PartBuilder
PartBuilder extracts pin-data for electronic components from a wide variety of sources and creates schematic symbol files used by popular industry EDA tools including:
- Cadence Allegro-HDL
- Cadence Orcad Capture and Orcad Capture CIS
- Mentor dxDesigner and Pads Professional
- Zuken
- Cr-5000 and Cr-8000
- cadStar
- Altium
What differentiates partBuilder from other symbol building tools are the extensive pin-data extraction capabilities, Smart-Frac and the Symbol Description Language (SDL).
Quick and accurate pin-data extraction is key to first time success in any board design project. PartBuilder can extract data from BSDL files, FPGA vendor files, existing symbol files and flexible spreadsheet formats provided by vendors or scraped from pdf datasheets.
The SDL enables the user to describe the layout of pins and symbols at a very high level. It supports looping constructs and pin-name pattern matching which provide capabilities that designers haven't seen before. For example using one 45 line SDL file, a user can create the symbol files for any Virtex7 FPGA in the Xilinx part family (some with over 2000 pins), and similar SDL files will provide support for Altera(Intel) and Lattice part families. Designers and Librarians with even a little bit of programming experience have been quick to recognize the power of SDL.
PartBuilder runs on Windows and Linux Platforms.