CE-HDL

Owned by Bill OLeary
Last updated: Nov 11, 2018

Page Map:

Expand all   Collapse all

On This Page:

Introduction to CE-HDL

CE-HDL provides a suite of efficiency plugins integrated into the AllegroHDL schematic capture tool

At the present time, 2 plugins are provided: PinWire and Align 



CE-HDL:PinWire   

  • The PinWire plugin provides the capability to instantly add large numbers of named wire connections to symbols in the schematic.
    • PinWire uses the symbol pinNames as a starting point to create the SIG_NAME property that gets attached to each wire.
    • The wires start at the component pin and can be terminated to OFFPAGES, IOPORTS, or selected versions of components like capacitors and resistors.
      • The OFFPAGE and IOPORT types are selected based on the pinType which is determined by reading the component library information.
    • The user may specify a prefix or suffix to be added to the SIG_NAME. 
    • The user can also provide a list of renaming rules to apply to create flexible SIG_NAMES per wire.
      • A set of rename rules can be created and stored for each component
    • PinWire can also use an FPGA Pin Report to find the proper SIG_NAME to attach to a wire connected to an FPGA Pin.
      • This feature alone can save hours to days worth of schematic capture work while also providing unparalleled accuracy.
    • The user can also use an interactive GUI to create and define the what nets  and voltages symbol power pins will be connected to.


CE-HDL:Align 

  • The Align plugin enables the user to align components, and netnames in their schematics providing a very efficient means to produce a polished, professional looking schematic in seconds.