There are many times when you can obtain a set of symbol files for a part that wasn’t built for your EDA tool or was not built using your library standards and requirements. In these situations, PartBuilder can be used to either reformat the existing symbol to match your library rules or convert the symbol from the EDA tool it was built for to your current EDA Tool.

Converting Symbols

PartBuilder can currently read existing symbols from Allegro HDL, Orcad-Capture, Siemens (Mentor) and Zuken CR-8000/CR-5000 EDA tools. It converts the input symbols into Symbol Description Language (SDL). It then uses the SDL to create the symbols for any of the Allegro HDL, Eagle, Orcad-Capture, Pads, Altium/PCAD, Siemens (Mentor) and the Zuken CR-8000/CR-5000 tools.

Supported PIN_REPORT_TYPES and PIN_REPORT file

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AHDL_SYMBOL_FILES

PIN_REPORT_FILE

The user provides one of the following as the input PIN_REPORT_FILE. PartBuilder has the intelligence to find the rest of the symbol files in the corresponding part_name directory.

1. part_name/chips/chips.prt

2. part_name/sym_x/symbol.css

3. part_name/part_table/part_table.ptf

ORCAD_SYMBOL_FILES

PIN_REPORT_FILE:

1. Ascii edif file exported from an OLB file

   1. if the edif file contains multiple library parts, the user will be prompted to pick one of the parts inside the

MENTOR_SYMBOL_FILES

PIN_REPORT_FILE:

1. This should point to one of the viewDraw formatted ascii files for the part. PartBuilder will ask for the base-name of the symbol files.

   1. Vdraw symbol files are stored for a part are stored in a single directory and are usually constructed like this: base_name_[sym1_name].1, base_name_[sym2_name].1… base_name_[symN_name}.1) in a single directory

ZUKEN_SYMBOL_FILES

PIN_REPORT_FILE:

1. Ascii .cdf file. The cdf file points to the ascii laf files which describe the pin arrangements around the symbols.

2. .prt file. This is a binary file, PartBuilder uses your installed Zuken conversion tools to convert this file to the ascii .cdf format and also converts the binary .smb symbol files to ascii .laf files.

Symbol Conversion Process Steps

Pin-Extract

The Pin-Extract step reads the symbol files and finds the Pin Name, Pin Number and Pin Type of each pin in every symbol. It sorts the pins by symbol, then by side (Left, Right, Top, Bottom) and then by their (X,Y) coordinate to provide Smart-Frac an easy path to creating the SDL files to describe the Symbols.

Symbol Dimension Spreadsheet

As part of the Pin-Extract process, PartBuilder creates a spreadsheet that allows the user to rebuild the symbols with the same dimensions as the original symbol.

Smart-FRAC

Smart-FRAC processes the sorted pin lists produced by Pin-Extract and creates the Symbol Description Language (SDL) files required to tell partBuilder how to build the symbol(s) for the part.

Depending on the size of the input symbol, Smart-FRAC may build one SDL file with all the required pin-matches, or a top_level sdl file that includes a file for the pins in each of the symbols that will be created for the part.

Smart-FRAC creates the SDL in 2 passes, the first pass contains a single pin-match for every device pin, and single spacers for every empty grid. The second pass optimizes the SDL to make it much easier to edit. In the optimization step, individual pins are compressed into diff-pairs, busses, and busses of diff-pairs. Multiple Spacers statements are combined into one spacer command (or BALANCE_SYMBOL_SIDES directives if they can be)

If you are looking to duplicate pin placements from the original symbols, the SDL produced by Smart-Frac is ready to go. If you want to customize or change symbol and pin layouts, you can use the SDL-Editor to optimize the way symbols are drawn for your own purposes.

Smart-FRAC Configuration Settings (CSETS)

For optimal results, Smart-FRAC needs to be provided a few details about the way the input symbol was constructed. Smart-FRAC is looking to convert the (x,y) location of a pins to a virtual grid (x,y) grid

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1. SMART_FRAC_GRID_SPACE

This setting tells Smart-FRAC the x/y increment that is equivalent to one symbol grid point. Smart-FRAC has a different default setting for each EDA tool and will prompt the user to change this value if needed.

2. SMART_FRAC_SYM_PIN_SPACING

This setting tells Smart-FRAC how many grids to expect between symbol pins. If the input symbol uses double spacing between pins, this would be set to 2. Matching this CSET to the input symbol construction enables optimal SDL results.

For instance, if the input symbol uses double spacing between pins and this is CSET is set to 1, Smart-Frac will SDL, where each pin will be created with a pin-match and a spacer. This SDL is valid, but it is more difficult to edit (and Smart-FRAC will not be able group pins into busses and/or diff_pairs)

3. SMART_FRAC_SYM_SPACER_GRIDS

This setting tells Smart-FRAC how many grids are used for a spacer. It's rare that this would be set to more than 1.

SDL-MAP

The SDL-MAP step maps the pins found in the Pin-Extract step to the symbols described by the SDL created in the Smart-Frac step. It creates an internal vendor agnostic data-structure to guide the Symbol Creation Steps.

CREATE_SYMBOLS

In the final step of the Symbol Conversion Process, new symbols are redrawn for each of the enabled EDA tools using the Customer specific symbol library rules.

The original symbol properties are discarded and replaced with the customer property contents and locations.

Video Demonstration

Converting Orcad Symbol To Allegro HDL