The CadEnhance Symbol Description Language (SDL) enables the user to describe the layout of pins and symbols at a very high level. It supports looping constructs and pin-name pattern matching which enables features designers haven't seen before in symbol creation tools. For example using one 45 line SDL file, you can create the symbol files for ANY FPGA in the Xilinx Virtex7 part family (some with over 2000 pins), and similar SDL files will provide support for Altera(Intel) and Lattice part families. While very powerful, the SDL is also very intuitive and simple to create.
In these pages, we will cover the syntax and structure of the SDL, but in order to remove the intimidation factor, we will first show a simple Example
A Simple Example SDL File describing a Fake DRAM Part
The PIN_REPORT_FILE for these symbols was the SIMPLE_BGA format and contained is shown on the right
The SDL was created in Excel and saved off as a .csv file For partBuilder to read
The PartBuilder SYMBOL_PIN_LIMIT control was set to 76 when this part was built.
The Symbols are shown below.
SIMPLE_BGA PIN_REPORT_FILE
Any line starting with a '#' is a comment and is ignored by partBuilder
SDL contains Symbol_Name_Definitions, Match_Statements and Pin_Spacer commands. It can also include loop directives and variables but
The Match_Statements contain a locator, optional modifiers and a pin_match defintions.
In this file, the locators are in column B, the optional Modifiers are in Column C and the pin_match is in column E
The syntax for a match_statement is locator:opt_modifier:opt_modier=>pin_match
the first Symbol_Name_Definition. (SND) DRAM_ACTL_PINS= on row 3
It tells partBuilder to create a Symbol named DRAM_ACTL_PINS containing the pins that match the Match_Statements between row 4 and the ';' at row 13 which ends the Symbol_Definition
The 2nd SND, DRAM_DQ_PINS= starts at row 15 and ends at row 26
The 3rd SND, POWER= starts on line 22 and ends at line 25
The last one GROUND= starts at row 33 and ends at row 35
The GROUND Symbol_Name_Definition actually creates 2 symbols GROUND and GROUND_1 because while partBuilder is adding the GND pins to both sides of the symbol, it sees that the number of pins exceeds 76, so it creates a new symbol on the fly to honor the SYMBOL_PIN_LIMIT setting.
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