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Once the Structure is in place, the CadEnhance PartBuilder, CE-HDL tools CE_HDL and PartBuilder work best if you create the design from the bottom up.
The reccomended flow is to work in your top level design. For simplicity sake, we always name the top block:"top". On any page you want a top level block, place empty placeholders for blocks using the block→add command
Starting in the low level HBLOCKS, CE-HDL can be used to create wire names derived from the pinNames of the devices instantiated in those blocks. Any wire that gets connected to an io-port symbol will create a Port for the HBLOCK. Once the wires are created, PartBuilder can be run to create the symbol for the HBLOCK where the automatically named wire names are used to create port names on the HBLOCK. CE-HDL is then used to wire the HBLOCK symbol, where the connection names are created from the HBLOCK port-names, using simple prefixes or more complex rename rules to create unique names. In this way, the majority of the design connections are created using strong naming conventions where signal names can be traced back to the initiating pinNames. This provides great accuracy in the net-naming and lends itself well to automated checking.
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