The CadEnhance Symbol Description Language (SDL) Enables enables the Librarian or Engineer user to Describe describe the Layout layout of pins and symbols from at a very high level. It supports looping constructs and pin-name pattern matching which enables features designers haven't seen before in symbol creation tools. For example using one 45 line SDL file, you can create the symbol files a very functional set of symbols for ANY FPGA device in the Xilinx Virtex7 part FPGA family (some with over 2000 pins), and similar . Similar SDL files will provide support for Altera(Intel) and Lattice part families. While very powerful, the SDL is also very intuitive and simple to create.
Here In these pages, we will cover the syntax and structure of the SDL, but in order to remove the intimidation factor, we will first show a simple Example
A Simple Example SDL File
The contents of the SDL file shown on the Left guides partBuilder to Create the Symbols shown on the Right.
It is a mix of Symbol Name Definitions, Match Statements and Pin Spacer commands.
A Match Statement contains a locator, optional modifiers and a pin_match defintion
DRAM_PINS= on line 5 is the first Symbol Name Definition and starts a new Symbol named DRAM_PINS
The DRAM_PINS symbol ends with the ';' on line 17
The 2nd Symbol Declaration POWER= starts on line 22 and ends at line 25
The 3rd Symbol Declaration GROUND= starts on line 29 and ends at line 31
The 3rd Symbol Declaration actually creates 2 symbols GROUND and GROUND_1 because while partBuilder is adding the GND pins to both sides, it sees that the number of pins on the symbol exceeds the ControlSetting:SYMBOL_PIN_LIMIT which was set to 75 in this case and knows it has to start a new symbol to honor that setting.
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#SDL FOR FAKE DRAM PART
#start symbol named DRAM_PINS
DRAM_PINS=
left=>clk_p
left=>clk_n
!BALANCE_SYMBOL_SIDES+2
PSG_dq_w0:left=>dq[7:0]
left=>spacer[1:0]
clock:left=>dqs0
bubble:left=>enb_n0
PSG_dq_w1:right=>dq[15:8]
right=>spacer[1:0]
clock:right=>dqs1
bubble:right=>enb_n1
;
#end symbol named DRAM_PINS
#start symbol named POWER
POWER=
LEFT=>VCCD
RIGHT=>VCC
;
#end symbol named POWER
#start symbol named GROUND
GROUND=
BOTH=>GND
;
#end symbol named GROUND
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