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The CadEnhance Symbol Description Language (SDL) Enables enables the Librarian or Engineer user to Describe describe the Layout layout of pins and symbols from at a very high level.   It supports looping constructs and pin-name pattern matching which enables features designers haven't seen before in symbol creation tools. For example using one 45 line SDL file, you can create the symbol files a very functional set of symbols for ANY  FPGA device in the Xilinx Virtex7 part FPGA family (some with over 2000 pins), and similar . Similar SDL files will provide support for Altera(Intel) and Lattice part families. While very powerful, the SDL is also very intuitive and simple to create.

Here In these pages, we will cover the syntax and structure of the SDL, but in order to remove the intimidation factor, we will first show a simple Example

A Simple Example SDL File describing a useless FAKE_DRAM Part

The PIN_REPORT_FILE for these symbols was the SIMPLE_BGA format and contained the PINS shown to the right

The SDL was created in Excel and saved off as a .csv file For partBuilder to read

Any line starting with a '#' is a comment and is ignored by the SDL reader.

The contents of the SDL file shown on the left guides partBuilder to  create the symbols shown below

It is a mix of Symbol_Name_Definitions, Match_Statements  and Pin_Spacer commands.

A Match_Statement contains a locator, optional modifiers and a pin_match defintion 

DRAM_ACTL_PINS=  on row 3  is the first Symbol Name Definition and tells partBuilder to create a Symbol named DRAM_ACTL_PINS containing the pins that match all the Match_Statements

The DRAM_PINS symbol ends with the ';' on line 13

The 2nc Symbol Declaration DRAM_DQ_PINS starts at row 15 and ends at row 26

The 3rd Symbol Declaration POWER= starts on line 22 and ends at line 25

The 4th Symbol Declaration GROUND= starts at row 33 and ends at row 35

The GROUND Symbol Declaration actually creates 2 symbols GROUND and GROUND_1 because while partBuilder is adding the GND pins to both sides,

it sees that the number of pins on the symbol exceeds the ControlSetting:SYMBOL_PIN_LIMIT=76 which so it creates a new symbol on the fly to honor that setting.

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Schematic Symbols CreatedImage Removed

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