Symbol Description Language (SDL)

The CadEnhance Symbol Description Language (SDL) Enables the Librarian or Engineer to Describe the Layout of pins and symbols from a very high level. It supports looping constructs and pin-name pattern matching which enables features designers haven't seen before in symbol creation tools. For example using one 45 line SDL file, you can create the symbol files for ANY FPGA in the Xilinx Virtex7 part family (some with over 2000 pins), and similar SDL files will provide support for Altera(Intel) and Lattice part families. While very powerful, the SDL is also very intuitive and simple to create.

Here we will cover the syntax and structure of the SDL, but in order to remove the intimidation factor, we will first show a few examples

A Few Examples:

Example SDL File

#SDL FOR DRAM PART

#start symbol named DRAM_PINS

DRAM_PINS=
left=>clk_p
left=>clk_n
!BSS+2=>
PSG_dq_w0:left=>dq[7:0]
left=>spacer[1:0]
clock:left=>dqs0
bubble:left=>enb_n0
PSG_dq_w1:right=>dq[15:8]
right=>spacer[1:0]
clock:right=>dqs1
bubble:right=>enb_n1
;

#end symbol named DRAM_PINS

#start symbol named POWER 
POWER=
LEFT=>VCCD
RIGHT=>VCC 
;
#end symbol named POWER 

#start symbol named GROUND 
GROUND=
BOTH=>GND
;
#end symbol named GROUND

Schematic Symbols Created