Schematic Hierarchy from the Bottom Up

When creating an Allegro HDL Hierarchical Schematic, it is worth spending a fair amount of time planning the Hierarchical Structure. The design consists of a Top Level where  common circuitry and a mix of Hierarchical Blocks (HBLOCKS)  can be placed.  Each HBLOCK design may instantiate one or more more levels of Hierarchy.  When partitioned properly, the design is easy to work with and modify and allows easy substitution of key blocks and lends itself well to reuse in other designs, saving countless days of development.

Once the Structure is in place, the CadEnhance PartBuilder, CE-HDL and  the pkgAssistant tools work best if you create the design from the bottom up.

Instructions

1. Plan your Hierarchy
   1. It is important to keep several goals in mind when you plan your Hierarchy
      
      1. Efficiency of Creation
         1. Many first time Hierarchical designers go a little overboard and create too many hierarchical blocks (HBLOCKS) to try and solve the problem. They create one HBLOCK for every IC, and another HBLOCK  for every function. This becomes difficult to manage because a symbol mus be maintained for each block in the design, and connectivity changes can cause a nightmare ripple effect.
         2. Cadence has created more functional ports which help to handle the connectivity changes, but squeezing  many disparate signals into an all encompassing bus makes  the design harder to follow and verify.
         3. With good forethought, the number of HBLOCKS can be kept to a minimum so that design changes are easier to manage
      2. Placement of key design blocks
      3. Reuse
         1. If your Hierarchy is designed efficiently, the major blocks will lend themselves to reuse in multiple designs either in their exact form or with simple modifications. This can shave huge amounts of development time when adapting or advancing one design into another.
      4. Substitution
         1. An Intelligent Hierarchical Design will allow the user to substitute out Key functions by simply swapping an HBLOCK.
            1. This can provide incredible time savings  if you have to swap FPGA devices, families or vendors.
               1. An FPGA block with its power HBLOCK inside the block can be helpful here since the port names may not change, but the required power may be completely different. If we feed 12V and 3.3V and a set of enable signals into the FPGA HBLOCK, and have the power HBLOCK provide the more granular rails to the FPGA. The changes required at the high level block interfaces will be minimized.
      5. Don't be afraid of multiple levels, but don't go crazy with levels either.
         1. multiple HBLOCK levels can be very 
2. Create Top Level schematic 
   1. If you are starting from scratch
   2. If you are reusing blocks

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  Allegro-HDL Hierarchical Schematic Design (HSD) from the Bottom Up