The NetList Compare Operation identifies changes in connections between the 2 designs.
A sample report can be viewed here: net1_diff_net2.txt
The reports summarize the following Differences between the 2 design Part Lists:
- Added Nets
- Deleted Nets
- Renamed Nets
- Nets with Added Pins
- Nets with Deleted Pins
- Pins on New Nets
- Nets with Property Differences (Future Feature)
- Pins with Property Differences (Future Feature)
Added Nets
Identifies any Nets appearing in Design1 that did not appear in Design2
Added Nets
*** ***Nets Added in Design1 NetList *** -------------------------------------------------------------------------------------------- | Net Name | Number of Nodes | Pin List | -+------------------+-----------------+---------------------------------------------------+- | VREF_DQ_W23 | 14 | C14_W2.1,C14_W3.1,C2_W2.1,C2_W3.1,C8_W2.1, | | | | C8_W3.1,R46.2,R47.2,U1_W2.E1,U1_W3.E1,U2_W2.E1, | | | | U2_W3.E1,U3_W2.E1,U3_W3.E1 | | VREF_CA_W23 | 14 | C13_W2.2,C13_W3.2,C1_W2.2,C1_W3.2,C7_W2.2, | | | | C7_W3.2,R44.2,R45.2,U1_W2.J8,U1_W3.J8,U2_W2.J8, | | | | U2_W3.J8,U3_W2.J8,U3_W3.J8 | | VREF_DQ_W01 | 14 | C14_W0.1,C14_W1.1,C2_W0.1,C2_W1.1,C8_W0.1, | | | | C8_W1.1,R42.2,R43.2,U1_W0.E1,U1_W1.E1,U2_W0.E1, | | | | U2_W1.E1,U3_W0.E1,U3_W1.E1 | | VREF_CA_W01 | 20 | C13_W0.2,C13_W1.2,C1_W0.2,C1_W1.2,C64.1,C65.1, | | | | C67.1,C68.1,C7_W0.2,C7_W1.2,R20.2,R41.2,U1_W0.J8, | | | | U1_W1.J8,U2_W0.J8,U2_W1.J8,U3_W0.J8,U3_W1.J8, | | | | U7.Y7,U8.Y7 | -+------------------+-----------------+---------------------------------------------------+-
Deleted Nets
Identifies any Nets that appeared in Design2 that no longer appear in Design1
Deleted Nets
*** ***Nets Deleted from Design1 NetList *** ------------------------------------------------------------------------ | Deleted Net Name | Number of Nodes | Pin List | -+---------------------+-----------------+----------------------------+- | TPS3808_SENSE_12V | 4 | C55.2,R160.1,R161.1,U20.5 | | GPIOB19_NC | 1 | U4.G1 | | TPS3808_SENSE_3V3 | 4 | C40.2,R123.1,R124.2,U19.5 | | P0V9_REG_BOOT_RC | 2 | C354.2,R281.2 | | RST_DELAY_12V | 2 | C56.2,U20.4 | | RST_DELAY_3V3 | 2 | C41.2,U19.4 | | GPIOB39_NC | 1 | U4.H5 | | GPIOB36_NC | 1 | U4.E2 | | PSOC_P0_4 | 1 | U3.26 | | GPIOB15_NC | 1 | U4.J2 | | PWRGD_P0V9 | 3 | R125.1,R54.2,U19.3 | -+---------------------+-----------------+----------------------------+-
Renamed Nets
Identifies any Nets that have the same connections in the two Netlists but the nets have different names
Renamed Nets
*** ***Nets Renamed in Design1 NetList *** ---------------------------------------------------------------------------------------------- | New Net Name | Old Net Name | Pin List | -+--------------+--------------------------------+------------------------------------------+- | P1R5V_IND | UNNAMED_8_BYPASSCAPNPOL_I100_A | C25.1,C26.1,C27.1,C28.1,L1.2,NS6.1,R21.1 | -+--------------+--------------------------------+------------------------------------------+-
Nets with Added Pins
Identifies any Nets in Design1 that have more Pins than in Design2
Nets With Added Pins
*** ***Nets With New Pins Added in Design1 NetList *** ---------------------------------------- | Net Name | New Pins | -+----------+-------------------------+- | GND | R41.1,R43.1,R45.1,R47.1 | | P1R5V | R20.1,R42.1,R44.1,R46.1 | -+----------+-------------------------+-
Nets with Deleted Pins
Identifies any nets in Design1 Netlist that had pins removed
Nets with Deleted Pins
*** ***Nets With Pins Removed from Design1 NetList *** -------------------------------------------------------------------------------- | Net Name | Deleted Pins | -+------------------------+---------------------------------------------------+- | SGPIO_LOAD_B_3V3 | R502.2 | | SYS_CORE_TRI_N | R484.1 | | P1V8 | C184.2,C185.2,C791.2,L29.2,R479.2,R481.2,R484.2, | | | R503.1,R504.1,R507.1,R508.1,R518.2,R529.2 | | CSW0_Q0_CTRL_TYPE | R505.2 | | SGPIO_CLK_B_3V3 | R498.2 | | POWERLOSS_N | R481.1 | | PCIE_OSC_REF_VDD | C731.2 | | GND | C150.2,C153.2,C183.2,C184.1,C185.1,C219.2,C235.1, | | | C236.1,C280.1,C731.1,C788.1,C791.1,J12.1,J13.1, | | | J3.1,J6.1,U19.2 | | P3V3 | R274.2,R495.1,R498.1,R499.1,R501.1,R502.1,R505.1, | | | R506.1,U19.6 | | CSW0_Q0_BP_TYPE_1V8 | R507.2 | | SB6_CSW0_Q0 | R504.2 | | CSW0_Q1_CTRL_TYPE | R506.2 | -+------------------------+---------------------------------------------------+-
Pins on New Nets
Identifies any pins that moved to a different Net in Design2
Pins on New Nets
*** ***Pins On New Nets in Design1 NetList *** ---------------------------------------------------------------------------------- | New Net | Old Net | Pin List | -+-------------+-----------+----------------------------------------------------+- | VREF_CA_W23 | DDR3_VTT2 | C13_W2.2,C13_W3.2,C1_W2.2,C1_W3.2,C7_W2.2,C7_W3.2, | | | | U1_W2.J8,U1_W3.J8,U2_W2.J8,U2_W3.J8,U3_W2.J8, | | | | U3_W3.J8 | | VREF_DQ_W23 | DDR3_VTT2 | C14_W2.1,C14_W3.1,C2_W2.1,C2_W3.1,C8_W2.1,C8_W3.1, | | | | U1_W2.E1,U1_W3.E1,U2_W2.E1,U2_W3.E1,U3_W2.E1, | | | | U3_W3.E1 | | VREF_CA_W01 | DDR3_VTT2 | C65.1,C68.1,U8.Y7 | | VREF_DQ_W01 | DDR3_VTT1 | C14_W0.1,C14_W1.1,C2_W0.1,C2_W1.1,C8_W0.1,C8_W1.1, | | | | U1_W0.E1,U1_W1.E1,U2_W0.E1,U2_W1.E1,U3_W0.E1, | | | | U3_W1.E1 | | VREF_CA_W01 | DDR3_VTT1 | C13_W0.2,C13_W1.2,C1_W0.2,C1_W1.2,C64.1,C67.1, | | | | C7_W0.2,C7_W1.2,U1_W0.J8,U1_W1.J8,U2_W0.J8, | | | | U2_W1.J8,U3_W0.J8,U3_W1.J8,U7.Y7 | -+-------------+-----------+----------------------------------------------------+-
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