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For these cases the Smart SIG_NAME(s) Entry is optimized to do the required work .for the designer
This Entry enables the user to create powerful sequences of Signal Names (sigNames) to add to a selected group of device pins.
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For ease of use, pinWire supports many aliases for the same pin type.
Valid Prefix Strings
Direction | Valid Prefixes | resulting offpage | resulting IO PORT |
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Input | i:, in:, inp:, input | INPUT | Inport |
Output | o:, out:, output: | OUTPUT | outport |
Inout | i:io:bi | INOUT | inout |
Smart SIG_NAME(s) with one sigName in the entry
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This provides one effective way to wire power pins common power pins.
Smart SIG_NAME(s) with multiple sigNames in the entry
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If more pins are selected than the number of names in the Entry, the signal Name sequence will start over after the last name is used.
Wires Added using Entry i:sig1,o:sig2,io:sig3,o:sig4 | |
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Pin rectangle defined top to bottom | Pin Rectangle Defined Bottom to top |
Using the Existing NetName(s) sig Browser to create the Smart SIG_NAME(s) List
The Existing NetNames button can be used to browse the current signal names on the page (and this will soon be expanded to selecting all the unique signalNames in the working block)
The user can multi select (using ctrl-Click and shift-Click) in the displayed signalList and right-click to paste the names into the sigName Entry. They will be pasted in separated by commas in the order they appear in the browser List.
If the user wants to control the order the signal names get added, it works better to just double click a single Name from the list in the order they want, and each one signal will get added to the Smart SIG_NAME(s) entry in that order
Simple Ranges in the sigName
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Simple Ranges in the sigName
Busses can be created with ease using a simple range in the sigName. The user must pay attention to the direction the pin rectangle is created
for instance i:gpio[7:0] and surrounds 8 pins, the wires attached to the pins will be named
gpio7 down to gpio0
gpio[0:7] would add gpio0 up to gpio7for example if the user selects offpages as the component to add, and uses this SmartSigEntry
expanded to i:gpio7,i:gpio6,i:gpio5,i:gpio4,i:gpio3,i:gpio2,i:gpio1,i:gpio0 and then starts over at i:gpio7
top to bottom | bottom to top |
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Comma Separated Ranges
Multiple ranged sigNames can be separated by commas,
Here we show the resutl of i:gpio[3:0],out:gpio[7:4],io:gpio[15:8]
pinWire would add wires to 16 pins,
the first 4 with input offpages,
the next 4 with output offpages
and the last 8 with inout offpages
!SKIP some Pins
To skip wiring pins in between valid sigNames use !skip or !nc as a wire namesigName
i:gpio[3:0],!skip,o:gpio[7:4]
or
to skip multiple pins use the bussed form of !skip or !nc
i:gpio[3:0],!nc[3:0],o:gpio[7:4]
Multiple Ranges in one SigName
More powerful alternation can be specified in between the square brackets
[digit:digit] like [0:7] or [3:11] will expand to the full range of bus_numbers
[foo|bar|zed] using the '|' character will round robin from
foo to bar to zed and then back to foo
a common use of this is to add [p|n] which will alternate p then n for diff_pairs
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which then gets fully expanded to a sequence that can be used to wire a xilinx fpga for ddr4 memory
Using the Existing NetName(s) sig Browser to create the Smart SIG_NAME(s) List
The Existing NetNames button can be used to browse the current signal names on the page (and this will soon be expanded to selecting all the unique signalNames in the working block)
The user can multi select (using ctrl-Click and shift-Click) in the displayed signalList and right-click to paste the names into the sigName Entry. They will be pasted in separated by commas in the order they appear in the browser List.
If the user wants to control the order the signal names get added, it works better to just double click a single Name from the list in the order they want, and each one signal will get added to the Smart SIG_NAME(s) entry in that order
The user may also select a text file containing signal names
split by commas and by lines
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