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Interleaving Busses of Signals using Alternation with  inc_dec operators

Sometimes the user will need to interleave signals in a complicated sequence with the first 2 signals of one bus, 4 signals of the next bus, 1 signal of the next bus, 4 signals of the previous bus....

More advanced interleaved alternations available and are described in the help page for this entry

[dig1:dig2:inc_dec_op] range operator like:
in:pcie0_sw_rx[3:0:1][p|n],in:pcie1_sw_rx[3:0:1][p|n],

...

pcie0_sw_rx3p,pcie0_sw_rx3n
pcie1_sw_rx3p,pcie1_sw_rx3n
pcie0_sw_rx2p,pcie0_sw_rx2n
pcie1_sw_rx2p,pcie1_sw_rx2n
pcie0_sw_rx1p,pcie0_sw_rx1n
pcie1_sw_rx1p,pcie1_sw_rx1n
pcie0_sw_rx0p,pcie0_sw_rx0n
pcie1_sw_rx0p,pcie1_sw_rx0n
(the result of which is 2 busses of diff_pairs interleaved)

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Interleaving with Modifiers to the inc_dec_op

The increment operator can also provide a HI_NIB or LO_NIB modifier to tell it to use the upper 4 bits
or the lower 4 bits of a bus
io:dqs[3:0:1][c|t],io:dq[31:0:8:HI_NIB],!skip,in:dm_[3:0:1],io:dq[31:0:8:LO_NIB],
This expands to
io:dqs[3][c|t],dq[31:28],!skip,in:dm3,io:dq[27:24],
io:dqs[2][c|t],dq[23:20],!skip,in:dm2,io:dq[19:16],
io:dqs[1][c|t],dq[15:12],!skip,in:dm1,io:dq[11:8],
io:dqs[0][c|t],dq[7:4],!skip,in:dm0,io:dq[3:0],

which then gets fully expanded to a sequence that can be used to wire a xilinx fpga for ddr4 memory

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Using the Existing NetName(s) sig Browser to create the Smart SIG_NAME(s) List

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If the user wants to control the order the signal names get added, it works better to just double click  a single Name from the list in the order they want, and each one signal will get added to the Smart SIG_NAME(s) entry in that order

Smart SIG_NAME text file

The user may also select a text file containing signal names
split by commas and by lines

Smart SIG_NAME Perl File

If the user is comfortable using Perl, they can write a perl script to generate a string
of comma seperated separated signal names that must be assigned to the variable named \$expString.

In this case, the user is responsible to make sure the Perl compiles cleanly
or a warning will popUp that
may or may not be easy to figure out

When the user selects the Edit button next to the Smart SIG_NAME Entry, and the Entry is empty or does not point to a file,

They will be prompted to Pick a fileName to save to. 

If the file they choose ends in .pl, pinWire will create an empty template file with the following contents. 

#!/usr/bin/perl
use strict;
use warnings;
my $expString="";
#you need to create code that adds comma separated signal names to the $expString variable
#note that strict is enforced so you need to declare your variables with 'my'

#Insert code here


#End insert code

print "\$expString=$expString\n";
#this needs to be the last thing you do in this code

$expString=$expString;

the User should put their code to build the $expString in between the

#Insert code here 

and the

#End insert code

 Here is an example of some valid perl code which will build up a list of sigNames

#!/usr/bin/perl
use strict;
use warnings;
my $expString="";
#you need to create code that adds comma separated signal names to the $expString variable
#note that strict is enforced so you need to declare your variables with 'my'

#Insert code here
foreach my

...

 $i (0..3

...

){
  foreach my $j (0..1){
    foreach my $pn (qw(p n)){
      $expString.="I:pcie_sw" . $j ."_rx_" .${i} .${pn}. ",";
    }
  }
}
#End insert code

print "\$expString=$expString\n";
#this needs to be the last thing you do in this code

$expString=$expString;

Here is the resulting value of expString which pinWire will process in place of  the contents of the Smart SIG_NAME(s) Entry

$expString=I:pcie_sw0_rx_0p,I:pcie_sw0_rx_0n,
I:pcie_sw1_rx_0p,I:pcie_sw1_rx_0n,
I:pcie_sw0_rx_1p,I:pcie_sw0_rx_1n,
I:pcie_sw1_rx_1p,I:pcie_sw1_rx_1n,
I:pcie_sw0_rx_2p,I:pcie_sw0_rx_2n,
I:pcie_sw1_rx_2p,I:pcie_sw1_rx_2n,
I:pcie_sw0_rx_3p,I:pcie_sw0_rx_3n,
I:pcie_sw1_rx_3p,I:pcie_sw1_rx_3n,