...
To skip wiring pins in between valid sigNames use !skip or !nc as a sigName
i:gpio[3:0],!skip,o:gpio[7:4]
or
to skip multiple pins use the bussed form of !skip or !nc
i:gpio[3:0],!nc[3:0],o:gpio[7:4]
Multiple Ranges in one SigName
More powerful alternation can be specified in between the square brackets
[digit:digit] like [0:7] or [3:11] will expand to the full range of bus_numbers
[foo|bar|zed] using the '|' character will round robin from
foo to bar to zed and then back to foo
a common use of this is to add [p|n] which will alternate p then n for diff_pairs
...
Alternations with the '|' character
DiffPair signals are usually entered in sequence with sig1_p, sig1_n,sig2_p,sig2_n
The Smart SIG_NAME(s) entry easily supports this using a range with anything separated by the pipe '|' character
note here the sig1 and sig2 alternations are n|p and the sig3 alternation is p|n
The alterations are not limited to simple characters,
the user could enter o:led_[red|green|orange|purple|muave]
Multiple Ranges in one SigName
Multiple alternations in the sigName are handled gracefully.
The alternations are expanded in a loop type order where the rightMost alternation is the inner most loop
So a complex bus of diff pairs can be added like this:
pcie_[rxsw0|txsw1]_dq[3:0][p|n]
PinWire sees 3 alternations, the sw0|sw1 the 3:0 and the [p|n]
There are 3 alternations, the rightmost has 2 values, the middle one has 4 values and the leftmost has 2 valuesthis will expand to:
pcie_rx_dq3p pcie_rx_dq3n
pcie_rx_dq2p pcie_rx_dq3n
pcie_rx_dq1p pcie_rx_dq1n
pcie_rx_dq0p pcie_rx_dq0n
pcie_tx_dq3p pcie_tx_dq3n
pcie_tx_dq2p pcie_tx_dq3n
pcie_tx_dq1p pcie_tx_dq1n
pcie_tx_dq0p pcie_tx_dq0nso this will create a sequence of 2*4*2 or 16 sigName values
The first signame starts with the leftmost value of each alternation which is 'rx', '3' and 'p'
The resulting first signame in the sequence is: pcie_sw0_dq3p
then it cycles the rightmost alternation to 'n' to create: pcie_sw0_dq3n
then it cycles the rightmost alternation back to 'p' and bumps the middle alternation to '2' to create: pcie_sw0_dq2p
then pcie_sw0_dq2n
Here is a table of all the alternations and the resulting sigNames in sequence
alternation value | alternation value | ||||||||
|---|---|---|---|---|---|---|---|---|---|
| seq# | lt | mid | rt | sigName | seq# | lt | mid | rt | signame |
| 1 | sw0 | 3 | p | pcie_sw0_dq3p | 9 | sw1 | 3 | p | pcie_sw1_dq3p |
| 2 | sw0 | 3 | n | pcie_sw0_dq3n | 10 | sw1 | 3 | n | pcie_sw1_dq3p |
| 3 | sw0 | 2 | p | pcie_sw0_dq2n | 11 | sw1 | 2 | p | pcie_sw1_dq2p |
| 4 | sw0 | 2 | n | pcie_sw0_dq2p | 12 | sw1 | 2 | n | pcie_sw1_dq2p |
| 5 | sw0 | 1 | p | pcie_sw0_dq1n | 13 | sw1 | 1 | p | pcie_sw1_dq1p |
| 6 | sw0 | 1 | n | pcie_sw0_dq1p | 14 | sw1 | 1 | n | pcie_sw1_dq1p |
| 7 | sw0 | 0 | p | pcie_sw0_dq0n | 15 | sw1 | 0 | p | pcie_sw1_dq0p |
| 8 | sw0 | 0 | n | pcie_sw0_dq0p | 16 | sw1 | 0 | n | pcie_sw1_dq0p |
Alternation with inc_dec operators
Sometimes the user will need to interleave signals in a complicated sequence with the first 2 signals of one bus, 4 signals of the next bus, 1 signal of the next bus, 4 signals of the previous bus....
More advanced interleaved alternations available and are described in the help page for this entry
...