FPGA Information Files

Vendors like Xilinx, Lattice and Altera all provide Ascii text files that describe every pin for every FPGA/CPLD device they manufacture. We will use the Xilinx naming convention and call these a package file. Each vendors file format is different, and sometimes changes for the next generation of device they produce. CadEnhance keeps current with the formats and can gather all the pin data required to build a physical symbol by reading these package files. Creating a handler for a newer proprietary format is usually a very straightforward process and the partBuilder tool will be quickly updated as new formats arise. Package files are used in both the Physical and Logical flows.
A second set of files is produced as one of the final steps when compiling an FPGA design to provide the function required in the board design. These reports provide a map of which physical pins are used to provide the logical function.
For instance, let's say the user is designing the FPGA to interface to a memory. The IO_XXX_## pins from the physical file will be used to provide Address and Data, clock and control pins for the memory. The report files resulting from the FPGA design run will map the specific IO_XXX_## pins used for A[15:0], DQ[7:0], RD, WR, and CLK. In the logical flow, those pins will be used as the pin names of the device and the partBuilder tool uses the FPGA report file to gather that information. Several IO banks can be used to provide one logical function, and they would all be built into the same symbol instead of breaking up the symbols by IO Bank.