Smart SIG_NAME(s) Entry

There are many times the names of existing symbol pins do not work well to create an Intelligent signal name for its attached wire

For these cases the Smart SIG_NAME(s) Entry is optimized to do the required work for the designer

This Entry enables the user to create powerful sequences of Signal Names (sigNames) to add to a selected group of device pins.

Direction Prefixes

A direction prefix may be added to each SigName in the Smart SIG_NAME(s) Entry to override pinWire's buitin pinType detection of a component pin

and force pinWire to add the desired flavor of IO or OFFPAGE.

For ease of use, pinWire supports many aliases for the same pin type.

Valid Prefix Strings

Direction	Valid Prefixes	resulting offpage	resulting IO PORT
Input	i:, in:, inp:, input	INPUT	Inport
Output	o:, out:, output:	OUTPUT	outport
Inout	i:io:bi	INOUT	inout

Smart SIG_NAME(s) with one sigName in the entry

In its simplest use, it holds the value of a single signal Name which will be added to every pin captured in the selected pins rectangle defined by the user.

This provides one effective way to wire power pins common power pins.

Smart SIG_NAME(s) with multiple sigNames in the entry

The user can also enter a list of comma separated sigNames which will be added in the sequence they appear to the selected pins

The names are added in the order that the pins are captured in the selection rectangle made by the user

If the rectangle is defined from top to bottom, the wires will be named from top to bottom,

If the rectangle is defined starting at the bottom pin and going up the to top pin, the bottom pin gets the first name in the list and the top pin gets the last name.

If more pins are selected than the number of names in the Entry, the signal Name sequence will start over after the last name is used.

Wires Added using Entry i:sig1,o:sig2,io:sig3,o:sig4
Pin rectangle defined top to bottom	Pin Rectangle Defined Bottom to top

Simple Ranges in the sigName

Busses can be created with ease using a simple range in the sigName. The user must pay attention to the direction the pin rectangle is created

for instance i:gpio[7:0] will be expanded to i:gpio7,i:gpio6,i:gpio5,i:gpio4,i:gpio3,i:gpio2,i:gpio1,i:gpio0 and then starts over at i:gpio7

top to bottom	bottom to top

Comma Separated Ranges

Multiple ranged sigNames can be separated by commas,

Here we show the resutl of i:gpio[3:0],out:gpio[7:4],io:gpio[15:8]

!SKIP some Pins

To skip wiring pins in between valid sigNames use !skip or !nc as a sigName
i:gpio[3:0],!skip,o:gpio[7:4]
or
to skip multiple pins use the bussed form of !skip or !nc
i:gpio[3:0],!nc[3:0],o:gpio[7:4]

Multiple Ranges in one SigName

More powerful alternation can be specified in between the square brackets
[digit:digit] like [0:7] or [3:11] will expand to the full range of bus_numbers
[foo|bar|zed] using the '|' character will round robin from
foo to bar to zed and then back to foo
a common use of this is to add [p|n] which will alternate p then n for diff_pairs

Multiple alternations are handled gracefully

So a complex bus of diff pairs can be added like this:

pcie_[rx|tx]_dq[3:0][p|n]
this will expand to:

pcie_rx_dq3p pcie_rx_dq3n
pcie_rx_dq2p pcie_rx_dq3n
pcie_rx_dq1p pcie_rx_dq1n
pcie_rx_dq0p pcie_rx_dq0n

pcie_tx_dq3p pcie_tx_dq3n
pcie_tx_dq2p pcie_tx_dq3n
pcie_tx_dq1p pcie_tx_dq1n
pcie_tx_dq0p pcie_tx_dq0n

More advanced interleaved alternations available and are described in the help page for this entry

[dig1:dig2:inc_dec_op] range operator like:
in:pcie0_sw_rx[3:0:1][p|n],in:pcie1_sw_rx[3:0:1][p|n],

When pinWire sees the inc_dec_op in a bus range, it makes 2 passes,
Expanding the range with the inc_dec_op first to:

and then expands whats left to:

pcie0_sw_rx3p,pcie0_sw_rx3n
pcie1_sw_rx3p,pcie1_sw_rx3n
pcie0_sw_rx2p,pcie0_sw_rx2n
pcie1_sw_rx2p,pcie1_sw_rx2n
pcie0_sw_rx1p,pcie0_sw_rx1n
pcie1_sw_rx1p,pcie1_sw_rx1n
pcie0_sw_rx0p,pcie0_sw_rx0n
pcie1_sw_rx0p,pcie1_sw_rx0n
(the result of which is 2 busses of diff_pairs interleaved)

The increment operator can also provide a HI_NIB or LO_NIB modifier to tell it to use the upper 4 bits
or the lower 4 bits of a bus
io:dqs[3:0:1][c|t],io:dq[31:0:8:HI_NIB],!skip,in:dm_[3:0:1],io:dq[31:0:8:LO_NIB],
This expands to
io:dqs[3][c|t],dq[31:28],!skip,in:dm3,io:dq[27:24],
io:dqs[2][c|t],dq[23:20],!skip,in:dm2,io:dq[19:16],
io:dqs[1][c|t],dq[15:12],!skip,in:dm1,io:dq[11:8],
io:dqs[0][c|t],dq[7:4],!skip,in:dm0,io:dq[3:0],

which then gets fully expanded to a sequence that can be used to wire a xilinx fpga for ddr4 memory

Using the Existing NetName(s) sig Browser to create the Smart SIG_NAME(s) List

The Existing NetNames button can be used to browse the current signal names on the page (and this will soon be expanded to selecting all the unique signalNames in the working block)

The user can multi select (using ctrl-Click and shift-Click) in the displayed signalList and right-click to paste the names into the sigName Entry. They will be pasted in separated by commas in the order they appear in the browser List.

If the user wants to control the order the signal names get added, it works better to just double click a single Name from the list in the order they want, and each one signal will get added to the Smart SIG_NAME(s) entry in that order

The user may also select a text file containing signal names
split by commas and by lines

If the user is comfortable using Perl, they can write a perl script to generate a string
of comma seperated signal names that must be assigned to the variable named \$expString.

In this case, the user is responsible to make sure the Perl compiles cleanly
or a warning will popUp that
may or may not be easy to figure out.

my \$expString;
foreach my \$i (3..0) {
\$expString.=sprintf("dqs_c%d,dqs_t%d,dq[%d,%d],!skip,dm_%d,dq[%d,%d],",
\$i,\$i,
31-\$i*8,28-\$i*8,
\$i,
27-(8*\$i)
24-\$i*8
)
}
^,