Smart SIG_NAME(s) Entry

There are many times the names of existing symbol pins do not work well to create an Intelligent signal name for its attached wire

For these cases the Smart SIG_NAME(s) Entry is optimized to do the required work for the designer

This Entry enables the user to create powerful sequences of Signal Names (sigNames) to add to a selected group of device pins.

Direction Prefixes

A direction prefix may be added to each SigName in the Smart SIG_NAME(s) Entry to override pinWire's buitin pinType detection of a component pin

and force pinWire to add the desired flavor of  IO or OFFPAGE.

For ease of use, pinWire supports many aliases for the same pin type.

Valid Prefix Strings 

Smart SIG_NAME(s) with one sigName in the entry

In its simplest use, it holds the value of a single signal Name  which will be added to every pin captured in the selected pins rectangle defined by the user.

This provides one effective  way to wire power pins common power pins.

Smart SIG_NAME(s) with multiple sigNames in the entry

The user can also enter a list of comma separated sigNames which will be added in the sequence they appear to the selected pins

The names are added in the order that the pins are captured in the selection rectangle made by the user

If the rectangle is defined from top to bottom, the wires will be named from top to bottom,

If the rectangle is defined starting at the bottom pin and going up the to top pin, the bottom pin gets the first name in the list and the top pin gets the last name.

If more pins are selected than the number of names in the Entry, the signal Name sequence will start over after the last name is used.

Simple Ranges in the sigName

Busses can be created with ease using a simple range in the sigName. The user must pay attention to the direction the pin rectangle is created 

for instance i:gpio[7:0] will be expanded to i:gpio7,i:gpio6,i:gpio5,i:gpio4,i:gpio3,i:gpio2,i:gpio1,i:gpio0 and then starts over at i:gpio7

top to bottom	bottom to top

Comma Separated Ranges

Multiple ranged sigNames can be separated by commas,

Here we show the resutl of  i:gpio[3:0],out:gpio[7:4],io:gpio[15:8]

!SKIP some Pins

To skip wiring pins in between valid sigNames use !skip or !nc as a sigName
i:gpio[3:0],!skip,o:gpio[7:4]
or
to skip multiple pins use the bussed form of !skip or !nc
i:gpio[3:0],!nc[3:0],o:gpio[7:4]

Alternations with the '|' character

DiffPair signals are usually entered in sequence with sig1_p, sig1_n,sig2_p,sig2_n

The Smart SIG_NAME(s) entry easily supports this using a range with anything separated by the pipe '|' character

note here the sig1 and sig2 alternations are n|p and the sig3 alternation is p|n

The alterations are not limited to simple characters, 

the user could enter o:led_[red|green|orange|purple|muave]

Multiple Ranges in one SigName

Multiple alternations in the sigName are handled gracefully. 

The alternations are expanded in a loop type order where the rightMost alternation is the inner most loop 

So a complex bus of diff pairs can be added like this:

pcie_[sw0|sw1]_dq[3:0][p|n]

PinWire sees 3 alternations, the sw0|sw1 the 3:0  and the [p|n] 

There are 3 alternations, the rightmost has 2 values, the middle one has 4 values and the leftmost has 2 values

so this will create a sequence of 2*4*2 or 16 sigName values

The first signame starts with the leftmost value of each alternation which is 'rx', '3' and 'p'

The resulting first signame in the sequence is: pcie_sw0_dq3p

then it cycles the rightmost alternation to 'n' to create: pcie_sw0_dq3n

then it cycles the rightmost alternation back to 'p' and bumps the middle alternation to '2' to create: pcie_sw0_dq2p

then pcie_sw0_dq2n

Here is a table of all the alternations and the resulting sigNames in sequence

Interleaving Busses of Signals using Alternation with  inc_dec operators

Sometimes the user will need to interleave signals in a complicated sequence with the first 2 signals of one bus, 4 signals of the next bus, 1 signal of the next bus, 4 signals of the previous bus....

[dig1:dig2:inc_dec_op] range operator like:
in:pcie0_sw_rx[3:0:1][p|n],in:pcie1_sw_rx[3:0:1][p|n],

When pinWire sees the inc_dec_op in a bus range, it makes 2 passes,
Expanding the range with the inc_dec_op first to:

in:pcie0_sw_rx3[p|n],in:pcie1_sw_rx3[p|n],
in:pcie0_sw_rx2[p|n],in:pcie1_sw_rx2[p|n],
in:pcie0_sw_rx1[p|n],in:pcie1_sw_rx1[p|n],
in:pcie0_sw_rx0[p|n],in:pcie1_sw_rx0[p|n],

and then expands whats left to:

pcie0_sw_rx3p,pcie0_sw_rx3n
pcie1_sw_rx3p,pcie1_sw_rx3n
pcie0_sw_rx2p,pcie0_sw_rx2n
pcie1_sw_rx2p,pcie1_sw_rx2n
pcie0_sw_rx1p,pcie0_sw_rx1n
pcie1_sw_rx1p,pcie1_sw_rx1n
pcie0_sw_rx0p,pcie0_sw_rx0n
pcie1_sw_rx0p,pcie1_sw_rx0n
(the result of which is 2 busses of diff_pairs interleaved)

Interleaving with Modifiers to the inc_dec_op

The increment operator can also provide a HI_NIB or LO_NIB modifier to tell it to use the upper 4 bits
or the lower 4 bits of a bus
io:dqs[3:0:1][c|t],io:dq[31:0:8:HI_NIB],!skip,in:dm_[3:0:1],io:dq[31:0:8:LO_NIB],
This expands to
io:dqs[3][c|t],dq[31:28],!skip,in:dm3,io:dq[27:24],
io:dqs[2][c|t],dq[23:20],!skip,in:dm2,io:dq[19:16],
io:dqs[1][c|t],dq[15:12],!skip,in:dm1,io:dq[11:8],
io:dqs[0][c|t],dq[7:4],!skip,in:dm0,io:dq[3:0],

which then gets fully expanded to a sequence that can be used to wire a xilinx fpga for ddr4 memory

Using the Existing NetName(s) sig Browser to create the Smart SIG_NAME(s) List

The Existing NetNames button can be used to browse the current signal names on the page (and this will soon be expanded to selecting all the unique signalNames in the working block)

The user can multi select (using ctrl-Click and shift-Click) in the displayed signalList and right-click to paste the names into the sigName Entry. They will be pasted in separated by commas in the order they appear in the browser List.

If the user wants to control the order the signal names get added, it works better to just double click  a single Name from the list in the order they want, and each one signal will get added to the Smart SIG_NAME(s) entry in that order

Smart SIG_NAME text file

The user may also select a text file containing signal names
split by commas and by lines

Smart SIG_NAME Perl File

If the user is comfortable using Perl, they can write a perl script to generate a string
of comma separated signal names that must be assigned to the variable named \$expString.

In this case, the user is responsible to make sure the Perl compiles cleanly
or a warning will popUp that
may or may not be easy to figure out

When the user selects the Edit button next to the Smart SIG_NAME Entry, and the Entry is empty or does not point to a file,

They will be prompted to Pick a fileName to save to. 

If the file they choose ends in .pl, pinWire will create an empty template file with the following contents. 

#!/usr/bin/perl
use strict;
use warnings;
my $expString="";
#you need to create code that adds comma separated signal names to the $expString variable
#note that strict is enforced so you need to declare your variables with 'my'

#Insert code here


#End insert code

print "\$expString=$expString\n";
#this needs to be the last thing you do in this code

$expString=$expString;

the User should put their code to build the $expString in between the

#Insert code here 

and the

#End insert code

 Here is an example of some valid perl code which will build up a list of sigNames

#!/usr/bin/perl
use strict;
use warnings;
my $expString="";
#you need to create code that adds comma separated signal names to the $expString variable
#note that strict is enforced so you need to declare your variables with 'my'

#Insert code here
foreach my $i (0..3){
  foreach my $j (0..1){
    foreach my $pn (qw(p n)){
      $expString.="I:pcie_sw" . $j ."_rx_" .${i} .${pn}. ",";
    }
  }
}
#End insert code

print "\$expString=$expString\n";
#this needs to be the last thing you do in this code

$expString=$expString;

Here is the resulting value of expString which pinWire will process in place of  the contents of the Smart SIG_NAME(s) Entry

$expString=I:pcie_sw0_rx_0p,I:pcie_sw0_rx_0n,
I:pcie_sw1_rx_0p,I:pcie_sw1_rx_0n,
I:pcie_sw0_rx_1p,I:pcie_sw0_rx_1n,
I:pcie_sw1_rx_1p,I:pcie_sw1_rx_1n,
I:pcie_sw0_rx_2p,I:pcie_sw0_rx_2n,
I:pcie_sw1_rx_2p,I:pcie_sw1_rx_2n,
I:pcie_sw0_rx_3p,I:pcie_sw0_rx_3n,
I:pcie_sw1_rx_3p,I:pcie_sw1_rx_3n,