XILINX Package File

The Xilinx tool sets provide commands to generate their "package file" which contains the ascii description of all the pins in their part. In their ISE tool for parts up to the Virtex6 family, they provided a "partGen" command which was used to build the package file. The Vivado tool for the newer Virtex7 and Ultrascale provides the same functionality with a "write_csv" command.
The first 30+ lines of the Xilinx Package file generated for the XC7VX690TFFG1761 part is shown in the figure below. Each line contains all the required information for a pin, including the pin number, pad name, function name, I/O bank, and the pin delay for each pin which is needed in some high speed memory applications. The pins are also listed in the order they appear in the banks so when partBuilder reads the file, it maintains that order and allows the user to easily build a very functional symbol for the physical flow.

Figure 9 Xilinx package File for xc7vx690tffg1761