FPGA Information Files

FPGA PIN REPORT FILES

PACKAGE_FILES 

Altera, Lattice MicroSemi and Xilinx all provide ascii text files that describe every pin for the  FPGA/CPLD device they manufacture.

For ease of discussion, we will use the Xilinx naming convention and call these the  PACKAGE_FILE. 

Package files are used in both the FPGA_PHYSICAL and FPGA_LOGICAL flows.

VENDOR_PIN_REPORTS

The FPGA Vendor tools also produce a final compilation report which provides a map of which physical pins are used to provide the logical function. We refer to this file as the VENDOR_PIN_REPORT.

The VENDOR_PIN_REPORT is only  used in the FPGA_LOGICAL Flow 

Each vendors file format is different, and may change for the next generation of device they produce.

CadEnhance makes an effort to keep current with the newer formats, and can gather all the pin data required to build a physical symbol by reading these package files.

Creating a handler for a newer proprietary format is usually a very straightforward process and the partBuilder tool will be quickly updated as new formats arise.

FPGA_PHYSICAL FLOW

Altera, Lattice MicroSemi and Xilinx all provide ascii text files that describe every pin for the  FPGA/CPLD device they manufacture.

For ease of discussion, we will use the Xilinx naming convention and call these the  PACKAGE_FILE. Each vendors file format is different, and sometimes changes for the next generation of device they produce.

CadEnhance makes an effort to keep current with the newer formats, and can gather all the pin data required to build a physical symbol by reading these package files. Creating a handler for a newer proprietary format is usually a very straightforward process and the partBuilder tool will be quickly updated as new formats arise. Package files are used in both the vendor_PHYSICAL and vendor_LOGICAL flows.

In the vendor_PHYSICAL Flow, the PIN_REPORT FILE should be set to the PACKAGE_FILE

Altera/Intel

The Altera PACKAGE_FILE for a device can be downloaded from the Intel/Altera Website: 

https://www.intel.com/content/www/us/en/programmable/support/literature/lit-dp.html

Choose the TXT version of the Pinout File for the appropriate Family and Device

Working with the Altera Package File:

An Altera Package File will contain the pinout for all of the physical packages available for the selected Device, so the user must select the actual Package Code for the device they are building

PartBuilder stores the selected package in the ALTERA_PACKAGE CSET and will read the PACKAGE_FILE, find all available packages in the file and present the user with a menu to select the appropriate package if the ALTERA_PACKAGE is not set. 

This selection is available in the "More Pin Report Settings" Gui when the PIN_REPORT_TYPE is set to ALTERA_PHYSICAL or ALTERA_LOGICAL

Here is an example of the error the user would first encounter if they read the Altera PACKAGE_FILE without first setting the ALTERA_PACKAGE CSET

Note that the "More Part Config Settings Menu" is now named the More Pin Report Settings and is accessed as shown above.

Future Versions of PartBuilder will make this process more straight forward by prompting the User to Select the package file interactively if it has not been chosen.

Lattice

The Lattice package file for a selected device can be downloaded from the Lattice SemiConductor Website,

or it can be created locally using the Diamond Tool.

On the website, the files are called "Package Migration Files"

see 

Working with the Lattice Package File:

Package Files downloaded from the Lattice Website will contain multiple devices for each selected package type, so the user must select the appropriate Lattice Device.

PartBuilder will prompt the user to select the device if it has not been previously selected and stored in the PART_CONFIG file. 

MicroSemi/MicroChip

The MicroSemi PACKAGE Files are called Pin Assignment Tables and can be downloaded directly from the MicroSemi/MicroChip Website. 

They usually appear on the Product Family Page like shown here:

https://www.microsemi.com/product-directory/fpgas/1690-proasic3#proasic3-e

Xilinx

While Xilinx does provide access to text files describing the device pinouts on their website, the content in those files is not sufficient for partBuilder to create the symbols properly.

Instead, The Xilinx PIN_REPORT file must be created locally using the most current Xilinx ISE or Vivado tool.

ISE Tool

The ISE tool works with the older device families created before the Virtex7 family, Virtex6, Spartan6,  

The ISE tool provides a command line utility called partGen

Vivado Tool

The Vivado tool works with device families starting with the Virtex7 devices.

It is a simple process to create the package file, but you do need access to the Vivado tool, so the person responsible for the FPGA design might need to be consulted:

the final command after you create a project for the selected device is 

write_csv -force yourFileName.csv

Video showing use of Vivado to Create Package File for PartBuilder

FPGA_LOGICAL FLOW

When using the vendor_LOGICAL flow, schematic symbols for the part will be created using the Functional Pin Names instead of the Generic IO Bank pinNames,

In this Flow, PartBuilder needs both the VENDOR_PIN_REPORT  and the PACKAGE_FILE

The main PIN_REPORT_FILE should be the VENDOR_PIN_REPORT and the PACKAGE FILE is stored using the FPGA_PACKAGE_FILE entry available in the More PIN_REPORT Settings Gui

Altera/Intel

The Altera VENDOR_REPORT_FILE is the .pin file created by the Quartus Tool

The Lattice VENDOR_REPORT_FILE is the .pad file created by the Diamond Tool

MicroSemi/MicroChip

The MICROSEMI_LOGICAL flow can accept the Libero Pin Constraint file  or or the final Pin Report file created by the Libero Tool

Libero PDC File

The Libero Pin Constraint file is used to locate and constrain physical pin properties like IO Standard, Pullups, Drive Strength and Slew Rates

it is usually named something like designName.pdc and looks something like this:

Libero Pin Report File

The Libero Pin Report file is the final output of the Libero Tool after placing and routing the FPGA design

It contains a description of all the pins and the pin properties

It is named something like: designName_pinrpt_name.rpt, and looks something like this.

Xilinx

ISE 

The Xilinx ISE Tool (for older device families) produces a .pad file or .pad.csv file for the placed and routed design detailing the pin placements and physical parameters of the pins

Vivado

The Xilinx Vivado Tool provides a  TCL command (report_io)  to create the pin report,

This command can be entered interactively or included in a larger tcl script that many companies use to execute the full  place and route process for an FPGA design   

The output filename is an argument to the report_io command,  so it makes sense to name it "designName.pad" like in the ISE flow using the command like:

report_io -file "designName.pad" -format text

###Its important to note that PartBuilder only supports the "text" format (not the xml format) of this report.