PACKAGE_FILES
Altera, Lattice MicroSemi and Xilinx all provide ascii text files that describe every pin for the FPGA/CPLD device they manufacture.
For ease of discussion, we will use the Xilinx naming convention and call these the PACKAGE_FILE.
VENDOR_PIN_REPORTS
The FPGA Vendor tools also produce a final compilation report which provides a map of which physical pins are used to provide the logical function. We refer to this file as the VENDOR_PIN_REPORT.
Each vendors file format is different, and may change for the next generation of device they produce.
CadEnhance makes an effort to keep current with the newer formats, and can gather all the pin data required to build a physical symbol by reading these package files.
Creating a handler for a newer proprietary format is usually a very straightforward process and the partBuilder tool will be quickly updated as new formats arise.
Package files are used in both the vendor_PHYSICAL and vendor_LOGICAL flows.
vendor_PHYSICAL
Altera, Lattice MicroSemi and Xilinx all provide ascii text files that describe every pin for the FPGA/CPLD device they manufacture.
For ease of discussion, we will use the Xilinx naming convention and call these the PACKAGE_FILE. Each vendors file format is different, and sometimes changes for the next generation of device they produce.
CadEnhance makes an effort to keep current with the newer formats, and can gather all the pin data required to build a physical symbol by reading these package files. Creating a handler for a newer proprietary format is usually a very straightforward process and the partBuilder tool will be quickly updated as new formats arise. Package files are used in both the vendor_PHYSICAL and vendor_LOGICAL flows.
In the vendor_PHYSICAL Flow, the PIN_REPORT FILE should be set to the PACKAGE_FILE
Intel/Altera
The Altera PACKAGE_FILE for a device can be downloaded from the Intel/Altera Website:
https://www.intel.com/content/www/us/en/programmable/support/literature/lit-dp.html
Choose the TXT version of the Pinout File for the appropriate Family and Device
Working with the Altera Package File:
An Altera Package File will contain the pinout for all of the physical packages available for the selected Device, so the user must select the actual Package Code for the device they are building
PartBuilder stores the selected package in the ALTERA_PACKAGE CSET and will read the PACKAGE_FILE, find all available packages in the file and present the user with a menu to select the appropriate package if the ALTERA_PACKAGE is not set.
This selection is available in the "More Pin Report Settings" Gui when the PIN_REPORT_TYPE is set to ALTERA_PHYSICAL or ALTERA_LOGICAL
Here is an example of the error the user would first encounter if they read the Altera PACKAGE_FILE without first setting the ALTERA_PACKAGE CSET
Note that the "More Part Config Settings Menu" is now named the More Pin Report Settings and is accessed as shown above.
Future Versions of PartBuilder will make this process more straight forward by prompting the User to Select the package file interactively if it has not been chosen.
Lattice
The Lattice package file for a selected device can be downloaded from the Lattice SemiConductor Website,
or it can be created locally using the Diamond Tool.
On the website, the files are called "Package Migration Files"
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Working with the Lattice Package File:
Package Files downloaded from the Lattice Website will contain multiple devices for each selected package type, so the user must select the appropriate Lattice Device.
PartBuilder will prompt the user to select the device if it has not been previously selected and stored in the PART_CONFIG file.
MicroSemi/MicroChip
The MicroSemi PACKAGE Files are called Pin Assignment Tables and can be downloaded directly from the MicroSemi/MicroChip Website.
They usually appear on the Product Family Page like shown here:
https://www.microsemi.com/product-directory/fpgas/1690-proasic3#proasic3-e
Xilinx
The Xilinx PIN_REPORT file must be created locally using the most current Xilinx ISE or Vivado tool.
The files available on the xilinx website do not provide enough information for PartBuilder to properly sort the IO_BANK pins.
ISE Tool
The ISE tool works with the older device families created before the Virtex7 family, Virtex6, Spartan6,
The ISE tool provides a command line utility called partGen
Vivado Tool
The Vivado tool works with device families starting with the Virtex7 devices.
It is a simple process to create the package file, but you do need access to the Vivado tool, so the person responsible for the FPGA design might need to be consulted:
Video showing use of Vivado to Create Package File for PartBuilder
vendor_LOGICAL
When using the FPGA_LOGICAL flow, PartBuilder uses both the PACKAGE_FILE and the PIN_REPORT_FILE These reports provide a map of which physical pins are used to provide the logical function.
For instance, let's say the user is designing the FPGA to interface to a memory. The IO_XXX_## pins from the physical file will be used to provide Address and Data, clock and control pins for the memory. The report files resulting from the FPGA design run will map the specific IO_XXX_## pins used for A[15:0], DQ[7:0], RD, WR, and CLK. In the logical flow, those pins will be used as the pin names of the device and the partBuilder tool uses the FPGA report file to gather that information. Several IO banks can be used to provide one logical function, and they would all be built into the same symbol instead of breaking up the symbols by IO Bank.
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