SMART-FRAC
SMART-FRAC
The SMART-FRAC Step analyzes the pinData and creates the Initial SDL Template file to let the user get started organizing the pins into symbols.
SMART-FRAC does things a little differently depending on what PIN_REPORT_TYPE the user has selected. There are 3 main types of PIN_REPORTS:
- FPGA Pin Reports
- XILINX, ALTERA, LATTICE and MICROSEMI PHYSICAL and LOGICAL Reports
- PinLocation Reports where SMART-FRAC can determine pinLocations from existing symbols or spreadsheets. These are the Symbol Conversion Flows
- MENTOR_SYMBOL_FILES
- AHDL_SYMBOL_FILES
- ORCAD_SYMBOLS
- ULTRA_LIB_PDT_TO_SYMBOLS
- INTEL_SYMBOL_INFO_CSV
- CADENCE_PART_DEVELOPER
- All Others
- BSDL_FILE
- IBIS_FILE
- GENERIC_CSV_FILE
- SIMPLE_BGA
- CHIPS_PRT_FILE
- ULTRA_LIB_PDT_TO_PINS
- AHDL_SCHEMATIC_BLOCK
- PIN_NUM_TYPE_FILE
If the PIN_REPORT_TYPE is one of the FPGA Pin Reports, Smart-Frac does extra work behind the scenes to group pins into symbols split by FPGA BANK.
If the PIN_REPORT_TYPE Is one of the symbol conversion Flows, Then SmartFrac will create an optimized SDL file that locates the pins in the internal symbol database just like they were located in the existing symbol.
In all other cases, Smart-Frac runs on the internal pin database and uses a proprietary advanced sorting algorithm to create the 2 SDL Template files.
- It finds and slices multi-level busses into manageable Chunks
- It finds and groups diff_pairs and adds the dpair modifier to reduce the amount of match_statements necessary to define the symbols
- It separates I/O and power signals into 2 groups of MATCH_STATEMENTS
- typically the POWER pins will not need to be sliced into smaller buses since they will just be added onto a symbol in large chunks
- typically the POWER pins will not need to be sliced into smaller buses since they will just be added onto a symbol in large chunks
- It auto assigns the left locator to inputs, the right locator to outputs and a CHOOSE_SIDE placeholder locator for all other signal types
These provide the user a head start to create the SDL
- auto_SDL_template.txt
- Plain text file for use with a text editor.
- auto_SDL_template.csv
- csv file to edit in EXCEL or another spreadheet editor
If no SDL file is selected in the SYMBOL_DESCRIPTION_FILE entry, PartBuilder will copy the auto_SDL_template.txt to a file called symbol_order_from_template.sdl, and set the SYMBOL_DESCRIPTION_FILE entry to point to that file. This gives the user the Intital Symbol Description Language file to work on.
The SDL creation process then becomes a matter of
- organizing the pre-generated MATCH_STATEMENTS into SYMBOL_DEFINTION wrappers
- changing the LOCATOR elements to place the pins onto the desired the side of the symbols
- adding SPACER directives to tweak the layout of the symbols
When the user goes to save the SDL file from the SDL-EDITOR PartBuilder checks to see if it is named "symbol_order_from_template.sdl" and if it is, it will prompt the user to save it as a new file name so that the working sdl file won't be overwritten the next time Smart-Frac Runs