Simple example of the Symbol Description Language


An example SDL file to describe a fictitious x16 DRAM Part

  • PartBuilder reads this 35 line SDL file and divides up the pins of this 200 pin DRAM into  5 schematic symbols.
  • The SDL File Is shown on the Left 
    • It was created in Excel and saved off as a .csv file for partBuilder to read.
      • Excel makes it easy to build logical looking MATCH_STATEMENTS broken across multiple columns
      • When PartBuilder reads the .csv file, it recombines all the columns to create a single MATCH_STATEMENT 
    • Its purpose is to tell partBuilder how to arrange all the part pins found in the PIN_REPORT_FILE into symbols
  • The PIN_REPORT_FILE for this part uses the SIMPLE_BGA PIN_REPORT_TYPE,  and is shown on the right
  1. The SDL contains SYMBOL_NAME_DEFINITIONSMATCH_STATEMENTS  and SPACER_COMMANDS
    1. It can also include loop directives and variables but there are none present in this simple example
  2. SYMBOL_NAME_DEFINITION start with SymbolName= and are terminated with a ';'
    1. The first SYMBOL_NAME_DEFINITION is DRAM_ACTL_PINS=  on row 3  and ends with the ';' at row 13
      1. It tells partBuilder to create a Symbol named DRAM_ACTL_PINS containing the pins that match the MATCH_STATEMENTS between row 4 and row 13 
    2. The 2nd is  DRAM_DQ_PINS=  and starts at row 15 and ends at row 26
    3. The 3rd is POWER= and starts on row 28 and ends at row 31
    4. The last one is GROUND= and starts at row 33 and ends at row 35
  3. The MATCH_STATEMENTS contain a locator, optional modifiers and a pin_match definitions.
    1. The syntax for a MATCH_STATEMENT is locator:opt_modifier:opt_modifier=>pin_match
      1. In this file, the locators are in column B, the optional modifiers are in Column C and the pin_match is in column E
      2. For explanation purposes, each MATCH_STATEMENT is appended with  a comment #xxxxxx to describe its purpose
    2. The first MATCH_STATEMENT is left :dpair => ck_p on line 4 
SDL FILE

PIN_REPORT_FILE (PIN_REPORT_TYPE=SIMPLE_BGA )

SIMPLE_BGA File Containing the Pin Information


Screenshot of PartBuilder Tool 

Below is a screenshot of the PartBuilder Tool after building the parts using the example SDL FILE


Symbols Created

Below are the Symbols that PartBuilder created after reading the PIN_REPORT_FILE and organizing the symbols and pins according to the rules in the Example SDL File

Above each symbol is an expandable block which contains the MATCH_STATEMENTS that were found between the Start and End of the SYMBOL_NAME_DEFINITION

Schematic Symbols Created
Match_Statements
left:dpair=>ck_p #place ck_p/clk_n diff_pair on left
!BSS+1           #SPACER_COMMAND:balance both sides of symbol with one extra spacer
left=>a[15:0]    #place address bus a15..a0 on left
left=>spacer     #SPACER_COMMAND add spacer on left
left=>CS_n       #place cs_n on left
left=>CAS_n      #place cas_n on left
left=>RAS_n      #place ras_n on left
left=>WE_n       #place we_n on left
left= ODT        #place odt on left
Match_Statements
left=>VREF           #place Vref on left
!BSS+2               #SPACER_COMMAND balance left and right and add 2 extra spacers on both sides
left=>dq[7:0]        #add bus dq7..dq0 on left
left=>spacer[1:0]    #SPACER_COMMAND add 2 spacers on left
left:dpair=>dqs0_p   #add dqs0_p/dqs0_n diff pair on left
left:bubble=>enb_n0  #add enb_n0 with a bubble on the left
right=>dq[15:8]      #add bus dq15..dq8 on the right
right=>spacer[1:0]   #SPACER_COMMAND add 2 spacers on the right
right:dpair=>dqs1_p  #add dqs1_p/dqs1_n diff pair on the right
right:bubble=>enb_n1 #add enb_n1 with a bubble on the right
Match_Statements
LEFT=>	VCCD	#add all pins matching vdd on the left
RIGHT=>	VCC 	#add all pins matching vcc on the right



Match_Statements
BOTH=>GND  #add any pins matching GND equally on the left and right hand sides of the symbols
**Note that because the SYMBOL_PIN_LIMIT was set to 76,
partBuilder automatically created the second GROUND_1 Symbol 
after adding 76 pins to the first symbol


Download the example to try with PartBuilder

Attached is a zip file containing the example files needed to create the symbols

Download the file and extract the folder to your computer (a good place might be: C:/cadEnhance/workdir/myParts)

Select the symGenCtl.txt file from your new folder and double-click the BUILD_SYMBOLS operation.

If you want to modify the SDL, make a backup copy of the simpleBGA.xlsx file. Open the simpleBGA.xlsx file and go to the symbolOrder tab.  

Make your changes and then save the sheet as symbolOrder.csv

BETTER_FAKE_DRAM.zip