Xilinx Pad File

The Xilinx Pad File is the report generated after the FPGA design is compiled. It contains most of the information in the package file, but it adds more information about the way the pin gets used in the design, including the pin functional name, the IO Standard the pin is configured for, whether the pin has a pullup, pulldown or special termination. The partBuilder Logical Flow combines the information from the Pad File and the Package File to build a complete picture of the FPGA pinout.

Figure 10: Snippet of Xilinx Pad File