The CadEnhance Symbol Description Language (SDL) enables the user to describe the layout of pins and symbols at a very high level. It supports looping constructs and pin-name pattern matching which enables features designers haven't seen before in symbol creation tools. For example using one 45 line SDL file, you can create the symbol files for ANY FPGA in the Xilinx Virtex7 part family (some with over 2000 pins), and similar SDL files will provide support for Altera(Intel) and Lattice part families. While very powerful, the SDL is also very intuitive and simple to create.
In these pages, we will cover the syntax and structure of the SDL, but in order to remove the intimidation factor, we will first show a simple Example
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AAllegro-HDL Hierarchical Schematic Design (HSD) from the Bottom UpAre you Using Hierarchical Designs? I find it incredible that in 2019, one year out from 2020, most Allegro Design Entry HDL customers seem to avoid Hierarchical Schematic Design (HSD) like the plague. The next tier of customers are starting to test HSD
AllegroHDL Specific CSETS to change symbol appearance
Search for AHDL CSETS Use the search function to find all csets with AHDL image2019-1-28_8-17-19.png image2019-1-28_8-3-7.png Property Control and locations AHDL_PN_PROP_TEXT_SIZE AHDL_PIN_NAME_TEXT_SIZE AHDL_PN_PROP_TEXT_SIZE AHDL_CNAME_OFFSET_FROM_BODY
Altera .pin File
Altera produces the .pin file as the report showing pin usage and configuration as a result of the user design. This file is analogous to the Xilinx .pad file, and in used by PartBuilder along with the Pins.txt file for the Altera Logical Flow to build a
Altera Pins.txt File
Like Xilinx, Altera provides a full text file to describe the pins of their FPGAs. Each FPGA Family of parts such as the Stratix IV, Stratix V, Arrria 10 has a slightly different format. The Text file is available for download on the Altera website. Alter
Archive Working Directory Tool
The Archive Working Directory Tool is a helpful new addition to the CadEnhance software suite that allows users to easily archive their working directory or extract a previously archived working directory. This tool is especially useful for sharing files
ASSIGN_PIN_DELAYS MACRO
The ASSIGN_PIN_DELAYS MACRO tells dal constraints to add pin_delay information from a spreadsheet type file for a list of Reference Designators in your design @self image2019-4-4_7-11-22.png REF_DES The REF_DES Attribute is a comma separated List of patte
AUTO_ASSIGN_VOLTAGE MACRO
The AUTO_ASSIGN_VOLTAGE MACRO is used to assign a VOLTAGE property to each target Net. Voltages are important when using signal Integrity Models. They can be entered in the schematic using a property, but many organizations do not take advantage of this,
AUTO_BUILD_DIFF_PAIRS MACRO
The AUTO_BUILD_DIFF_PAIRS MACRO tells dal constraints to perform an exhaustive search across all nets in the design to identify and create diff Pairs dal Constraints will identify the 2 members of the diff_pair and create a diff_pair root_name to assign
AUTO_IDENTIFY_PIN_DIR MACRO
The AUTO_IDENTIFY_PIN_DIR MACRO is used to force PinTypes for the Drivers and Receivers on an existing net Correct pinType definitions are very important for DIFF_PAIR constraints and when using Signal Integrity Models in simulation. The pinType definitio
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BBOM Header ConfigBOM Header Config: image-20220629-180630.png The BOM Configuration can be done in this menu, to allow for operations to ignore rows, require columns, and read columns correctly by selecting the proper header. This menu can be opened by clicking either BOM
BSDL FILE
Many High Pin count devices have JTAG pins to allow board level connectivity testing between device pins. In those cases, the vendor needs to provide a BSDL file to describe the pins. Vendors like Broadcom, Freescale, Marvell, and Avago to name a few prov
Build and look at the finished symbols
First we save the modfied sdl as a new file called second_symbol_order.sdl second_symbol_order.sdl And we get prompted to change the selected SYMBOL_DESCRIPTION_FILE CSET too match the new one Then we go through the build process and then view the new s
Build the First Pass of the Part
Once we have cleaned up the SDL and gotten rid of all the CHOOSE_SIDES modifiers we can create the Symbols for the Parts This video will show what it looks like when we have a CHOOSE_SIDE modifier left in the SDL (we intentionally put one back) and then w
BUILD_ECS MACRO
The BUILD_ECS MACRO Creates a Named ELECTRICAL_CONSTRAINT_SET (ECS) which can be applied to matching NetNames @self image2019-4-1_6-13-19.png image2019-3-31_8-43-25.png Electrical Constraint Sets An Electrical Constraint Set (ECS) is use to constrain the
BUILD_MIN_MAX_PROP_DELAY MACRO
The BUILD_MIN_MAX_PROP_DELAY MACRO is used to create a PROPAGATION_DELAY constraint for a group of nets where you need to constrain the min and max length of the nets Refer to the Propagation Delay Section in the Allegro ConstraintCore Documentation for m
BUILD_MULTI_RPD MACRO
The BUILD_MULTI_RPD MACRO is used to create a collection of RELATIVE_PROPAGATION_DELAY (RPD) constraints for a group of nets that must be routed as a MATCH_GROUP with a tolerance to a reference net. This makes efficient work of creating RPDS for the multi
BUILD_PCS MACRO
The BUILD_PCS MACRO Creates a Named PHYSICAL_CONSTRAINT_SET (PCS) which can be applied to matching NetNames or referenced by an Electrical Constraint Set (ECS) @self image2019-3-29_7-54-57.png Physical Constraint Sets A Physical Constraint Set is use to c
BUILD_SCS MACRO
The BUILD_SCS MACRO Creates a Named SPACING_CONSTRAINT_SET (SCS) which can be applied to matching netNames @self image2019-4-2_7-47-27.png SPACING Constraint Sets (SCS) A SPACE Constraint Set is used to constrain the LINE_TO_LINE attributes of signals on
BUILD_SINGLE_RPD MACRO
The BUILD_SINGLE_RPD MACRO is used to create a RELATIVE_PROPAGATION_DELAY (RPD) constraint for a group of nets that must be routed as a MATCH_GROUP with a tolerance to a reference net. Refer to the Relative Propagation Delay Section in the Allegro Constra
BUILD_STACKUP_FROM_FILE MACRO
The BUILD_STACKUP_FROM_FILE MACRO Provides an interface to the powerful new dal Stackup Tool. It points to the Stackup Spreadsheet that dal Stackup will read and Tells the dal constraint tool to read in the stackup spreadsheet Click here to download the s
BUILD_TOTAL_LENGTH MACRO
The BUILD_TOTAL_LENGTH MACRO is used to create a TOTAL_ETCH_LENGTH constraint for a single net or group of nets where you need to constrain the min and max length of the nets Refer to the Propagation Delay Section in the Allegro ConstraintCore Documentati
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CCadence Allegro Constraint System Reference InformationThe Cadence Allegro Constraint System has many details that are well covered in the Allegro Documentation. It would be a mistake to try and reproduce that documentation in this user guide. Instead we provide references to the actual Allegro Documents. Th
CadEnhance Common Tool Information
The CadEnhance tool set is built from a common code base, and many of the tools share the same features. This section is written to avoid duplicating instructions for each tool. @self
CadEnhance Product Documentation
bill banner.jpg Quick Navigation @self
Cadstar RINF Netlist
Example CadStar (RINF) File Below is a sample CadStar RINF file created by NetBom from an AllegroHDL netlist. The RINF has been edited to compress most of the information in order to provide a summary of the contents and structure of a typical RINF file f
Capacitance Report (Power Rail Summary)
When processing a design, NetBom will automatically generate a power rail summary report. This report consists of one page for each power rail that was able to be identified in the design, and each page contains a list of the capacitor parts and informati
Caps Over Voltage Report
One of the many useful features of our capacitance report is the ability to identify and highlight rail capacitors that have a part voltage that is incompatible with the voltage of the power rail that it is on. Below is a screenshot of a power rail on our
CE-HDL
Page Map: @self On This Page: 23-10-2018-08-43-42.png Introduction to CE-HDL CE-HDL provides a suite of efficiency plugins integrated into the AllegroHDL schematic capture tool At the present time, 2 plugins are provided: PinWire and Align CE-HDL:PinWire
CE-HDL Debug Console and Messages
Enabling or Disabling the Debug Console in the Windows version. When the windows version of AllegroHdl starts the ceHDL tool, it can be configured to open a debug console which displays status messages as the cadEnhance tools control the AllegroHDL sessio
CE-HDL SLIDE SHOWS
PowerPoints relating to CE-HDL Right Click and select "Save Link As..." to download Click to view Slides (without animation or video) Introduction to CE-HDL with Videos Note to see the videos you will need to download the powerPoint and present the slide
CE_INSTALL
Installing CeHDL The CE_INSTALL tool must be run at least once to integrate the CeHDL tool into the AllegroHDL environment. On a windows platform, the ce_install tool is located in the CE_ROOT_DIR/tools/CE_INSTALL/ce_install.exe. On a linux platform, the
CHIPS_PRT_FILE
The CHIPS_PRT_FILE flow uses the Chips.prt file from an ALLEGRO-HDL symbol. The PIN_NUM, PIN_NAME are found included in this file and PartBuilder knows how to read and extract that information. The PIN_TYPE can also be encoded in the File. This is used by
Configuration Settings HTML Report
Configuration Settings HTML Report With each release of the CadEnhance Tools, there is a good chance that a new set of Configuration Settings (CSETS) have been added or removed. Rather than maintain the documentation of these CSETS in this central documen
Configuration Settings in CadEnhance Tools
CONFIGURATION SETTINGS (CSETS) All CadEnhance Tools Use CONFIGURATION_SETTINGS (CSETs) to store options and control tool behavior. A CSET is a named storage item used by the tool to control important functions. They can be used to store a file_name, a di
Configure the expected pins
1. Select the More PIN_REPORT Settings... We press this button to open up a new GUI where we can enter more configuration settings (CSETS) 2. Setup the PCHK_DEVICE_PIN_NUMBERS Entry In this step we tell partBuilder what Pins to expect from the device Pin
Control Files
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Copy Final Symbols to Release Directory
CREATE_SYMBOLS image2018-10-31_16-56-17.png CREATE_SYMBOLS Build Symbol Files for Each Enabled EDA Tool Final Save Operations Report Warnings
Creating a SpreadSheet from a PDF File
Some Vendors will provide the user with a nicely formatted Pin Data spreadsheet which is very easy to use with the PartBuilder SPREADSHEET PIN_REPORT_TYPES. Others will only provide the pinData in a PDF datasheet. Extracting pinData from the PDF file can
Cross Probe Marker Files
Working with the NetBom Marker files When you want to cross probe a NetBom Report Item to see it in the schematic or PCB, NetBom builds a special marker file that can be used in the specific schematic or board tool. Cross Probing from the Report Item Cont
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DdalTools constraint ToolThe Allegro PCB Constraint System is a very powerful, flexible tool which is required to properly constrain today's high speed PCB designs. Without it, the detailed manual checking required to create a successful high speed PCB design quickly becomes an u
Design Audit Reports
We will fill this section with general documentation for the design audit reports.
Design Comparison and Conversion CSETs
This section discusses some of the CSETS that Affect the Design Comparison KEY_PROP_LIST/KEY_PROP_IGNORE_LIST image2019-8-26_13-14-17.png When Reading the Input Design Files, NetBom automatically builds a list of ALL the part and net properties it finds a
Design Comparison Operations
When the user selects the Diff Netlists operation, NetBom will read the netlist file(s) for the selected designs. It creates a database for each design and then intelligently compares the items and generates report tables concisely detailing the differenc
Directory Cleanup Utility
The Directory Cleanup Utility allows users to easily remove unimportant output and junk files from their working directory. The tool displays a tree file structure that is automatically populated with recommended files to be removed. View the video demo h
Download and extract tools
Download and extract tools The CadEnhance Toolset can be downloaded from the CadEnhance Website using the following link: https:// https://www.cadenhance.com/free-tool-downloadswww.cadenhance.com/downloads https://www.cadenhance.com/downloads A table is p
Download the IBIS Model from Micron Website
The next step is to acquire the IBIS model for the DDR3 Dram Device We will use the Micron MT41K512M16Ha-125 device Here is a link to the device product page https://www.micron.com/products/dram/ddr3-sdram/part-catalog/mt41k512m16ha-125 https://www.micro
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EEDA Symbol ConversionThere are many times when you can obtain a set of symbol files for a part that wasn’t built for your EDA tool or was not built using your library standards and requirements. In these situations, PartBuilder can be used to either reformat the existing symb
Edit Part Properties
EndPoint Compare Operation The NetBom EndPoint Compare operation enables the user to cross-check connections between two endpoints in two different netlists. The common usage of this is to verify connections made between connectors in 2 designs. Use Case Let's say you have a mother
EndPoint Compare Reports
The EndPoint Compare operation will produce two reports: one Excel report and one interactive web report. The report headers in this report, like all NetBom web browser reports, are customizable using the NETBOM_REPORT_SETTINGS CSET https://cadenhance.atl
EndPoint Verify Operation
The NetBom EndPoint Verify operation enables the user to validate connections made to a list of endpoints in the selected netlist. NetBom can compare the net names and properties such as voltage attached to the pins/wires of each selected endpoint to the
EndPoint Verify Reports
The EndPoint Verify operation generates two types of reports. The first is an Excel file and the second is our interactive web report. The report headers in this report, like all NetBom web browser reports, are customizable using the NETBOM_REPORT_SETTING
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FFeed-Thru Pin MappingThe feed-thru pin mapping feature allows the user to define sets of pins that should be traced through by NetBom Net Tracing. These sets can be configured in a number of ways: by part number, part name, part type; and from pin number to pin number or pin
File lists
First Look with Pin Explorer 1. Press the Exlpore Pins Button We will see the pins partBuilder extracted from the IBIS FILE 2. The Pin Explorer pops up we can see an ALL_POWER_PINS Pin group and we press the '+' to collapse it 3. Next we collapse the ALL_SIGNAL_PINS PIN_GROUP Improv
First pass at modifying the SDL file with SDL-Editor.
Now we will go through the steps of modifying the SDL to create the Symbols that we want to create @self Its helpful to look at what we are trying to achieve first: FIRST PASS We will create 2 symbols, one with the ADDRESS/CONTROL and DATA pins on one sym
FPGA Pin-Data Files
There are 2 Supported Flows for FPGA symbol Creation The FPGA_PHYSICAL and FPGA_LOGICAL flows. The user selects the Flow using the PIN_REPORT_TYPE entry with the vendor_PHYSICAL or vendor_LOGICAL selections image2019-9-5_8-22-27.png FPGA PIN REPORT FILE
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GGENERIC_CSV_FILE Example 1Here is a sample file that was created from a Vendors pdf datasheet for a DDR4 DIMM using the Nitro Free PDF to Excel Converter https://www.pdftoexcelonline.com In this case the spreadsheet provides the PIN_NUMBER in columns A,C,E,G,J,L,N,and P and the
GENERIC_CSV_FILE example 2
The following link can be used to download a zipped folder containing all the files needed to experiment with this example: ATMEGA328P_AU_MLF32_GCSV_EXAMPLE.zip (Note the user should choose the symGenCtl_mlf32.txt as the PART_CONFIG_FILE) Here is another
GENERIC_CSV_FILE Example 3
The following link is a zip file that contains all the files necessary to build this example part :LMK00338_GENERIC_CSV.zip This file for a TI LMK00338 PCIE Clock generator was converted from pdf using the nitrocloud https://www.pdftoexcelonline.com/ http
GUI Tricks and Tips
Helpful Key Bindings when editing a GUI Entry image-20210121-230708.png When entering values in an Entry like the PinMatch/Label Fields in the Legacy SDL Editor, or in any CSET Entry Field, there are many key useful key short cuts that do not match the no
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HHelpful Videos for CE-HDLThis table provides a list of Helpful Videos that can be used to learn some of the features of the CE-HDL Tool Link Description CadEnhance ScreenCast Video Channel http://scast.cadEnhance.com This is a link to all the public CadEnhance ScreenCast Videos S
Helpful Videos for PartBuilder
These tables provide lists of Helpful Videos that can be used to learn to work with the PartBuilder Tool GENERAL VIDEOS Link Duration (mm:ss) Description CadEnhance ScreenCast Video Channel http://scast.cadEnhance.com This is a link to all the public CadE
How PinWire chooses the SIG_NAME to add to each pins wire
When the user starts the PinWire operation with the 'RUN' button and define the set of pins to wire, PinWire goes through a step by step process to determine the SIG_NAME it will add to the wire it attaches to the pin. PinWire reads the symbol File to fin
How To Create IBIS Models for Intel Agilex Family of Devices
How to Build IBIS Models for Intel® AgileX® FPGA Designs — CadEnhance https://www.cadenhance.com/blog/how-can-i-build-an-ibis-model-for-the-new-intel-agilex-fpga-design
How-to articles
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IImportant Configuration Settings (CSETS) that were changedEntry Contents Purpose Notes SIG_RENAME_RULES DQS$:DQS_P,CK$:CK_P,#$:_N,A10:A10_AP,A12:A12_BC_N changes any pin ending in # to _N adds P to any pin ending in CK (so CK->CK_P) adds P to any pin ending in DQS (so LDQS->LDQS_P) they can be identified as di
Importing Partlist Properties From External Datasource
The PART_PROPERTY_DB_FILE configuration setting (CSet) allows you to import part properties from a spreadsheet file or a SQL database. If you leave this setting blank, NetBom will not import any extra part properties. The CSet PART_NUMBER_PROPS is used to
Input Netlists
This section discusses the Input Netlist Formats and the CSETS that modify the behavior of NetBom when processing them. BOM SpreadSheets NetBom added support to read Generic BOM Spreadsheets In Version 21.12.1 A BOM SpreadSheet can be compared to another
Install License File
Install the License File Place the license.dat file in the ROOT:\cadenhance\license directory In this case ROOT is C:\ image2017-2-3_18-28-13.png You should now be able to operate the Tools.
Installation Instructions
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Installing Multiple Versions of CadEnhance Tools
Multi Version Installation It can be very useful to install each version of the tools in its own directory so that users can revert to an older version of the tool if necessary. At CadEnhance we use this technique so that we can easily switch to a custome
Interactive Design Review
Overview Every report in NetBom is equipped with a variety of Interactive Design Review features. These features serve to enable the user to have a rich set of review tools available at all times. After a design has been reviewed, the review data can be s
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LLattice CPLD filesMuch like Xilinx and Altera, (very much like Xilinx) Lattice has a special file to describe the physical pins and a post compilation file (called a .pad file) to describe the pins usage. Part Builder can read these files to produce a physical CPLD symbol
Look at First Pass of Symbols vs SDL
In this video we look at the symbols that were created and compare them with the SDL in the SDL file We use the text editor to look at the SDL file because we can see alot more of the lines without the widgets that take up alot of space in the SDL editor
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MMAP_PINS_TO_SYMBOLSMAP_PINS_TO_SYMBOLS image2018-10-31_16-57-34.png In the MAP_PINS_TO_SYMBOLS Operation, PartBuilder reads the Symbol Description Language (SDL) file and uses it to assign the pins extracted in the READ_PIN_REPORT operation to the appropriate sides of the d
Move the Data Pins to a new Symbol
Here we will edit the SDL to move the Data Pins to a new Symbol First we rename the ALL_SIGNAL_PINS symbol placeholder to ADDRESS_CTL_PINS Its as easy as inserting an End of Symbol marker before the BALANCE_SYM_SIDES directive we had used to separate the
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NNet Trace Window AnatomyOverview The Net Trace window can be opened from any web report that contains nets with tracing data. Right-click any row to open the context menu, and select the net tracing option. Below is a sample image of a simple trace that is rendered in the net tr
Net Tracing
Summary NetBom provides a set of tools that allows users to trace all the connections in a given electronic design and display them graphically in a web browser. The tracing behavior can be customized using a set of configuration settings. This is useful
NetBom
CadEnhance_NetBom_Homepage-Image.png The NetBom tool from CadEnhance concisely documents the differences between revisions of Net Lists and Bills Of Materials (BOMs) of a PCB board design. It also produces Human Readable BOMs and helpful hyperlinked NetLi
NetBom Configuration Settings (CSETS)
Overview All CadEnhance Tools Use CONFIGURATION_SETTINGS to store options and control tool behavior. For efficiency’s sake, we will refer to individual CONFIGURATION_SETTINGS as a CSET. A CSET is a variable used by the tool and can be used to store a file
NetBom GUI
@self Main GUI image2022-6-29_11-53-13.png The Main GUI Provides the User a way to select the design NetLists to Compare designs and to see the status and Results of those Operations. Config File: image2022-6-29_11-54-3.png A CONFIG_FILE stores all the Co
NetBom Voltage Matching
Overview NetBom has a voltage detection system that uses pattern recognition to determine voltage values for nets and parts. Given that voltage naming conventions change frequently and vary based on customer and need, this system has been expanded to allo
NetList and PartList Conversion
The input netlist file contains verbose information about the design, including nets, net connections, net properties, pins and pin properties, and parts and part properties. The files are built for machine processing and are not friendly for user viewing
NetList Comparison Reports
The NetList Compare Operation identifies changes in connections between the 2 designs. The reports summarize the following differences between the 2 design part lists: Added Nets Removed Nets Renamed Nets Nets With Added Pins Nets With Removed Pins Nets W
NetList/BOM CSV Reports
Overview The netlist tool exports a partlist.csv and netlist.csv file using the same headers as the web browser report. Configuration information for this can be found in the NetBom Report Settings documentation. partlist.csv The headers option in the Net
Next Steps
This is a list of steps that we have not yet covered in the Tutorial We will use them as a guide to touch on specific points that we need to be aware of @self
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OOpen PartBuilder and Create New Part1. Press the Choose Button next to the PART_CONFIG_FILE 2. Select the "Create New Part Folder..." Menu Item 3. Make sure Create New Folder Radio Button is selected 4. Type DDR3_TUTORIAL in the NEW_PART_NAME Entry partBuilder will create a directory called
Organize the Data Pins and select a side for the pinMatches marked as choose side.
In this step we organize the DQ, DM and DQS pins We are putting the pins for the Lower Byte (DQ[7:0],LDM and LDQS) on the Left Side and the pins for the Upper Byte (DQ[15:8],UDM and UDQS) on the right Since SMART-Frac created only one Bus for DQ namely
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PPart Addition GuidePart Builder Operations @self image2018-10-31_16-22-10.png The BUILD_SYMBOL OPERATION List in the Middle of the Main GUI allows the user to select the processing steps required to build the schematic symbols for the current part Double Clicking BUILD_SYMBOLS will start the whole
Part Builder Pin-Extract Information Sources
@self PartBuilders Pin-Extract Function, is focused on obtaining Pin Information for an electronic component, quickly, efficiently and most important, accurately . At a minimum, the tool needs to gather the pin name, pin number, and pin type (input, outpu
Part Type Identification
Overview When processing the Parts In a Design, it is very useful to be able to assign a PART_TYPE based on properties extracted for each Part. NetBom provides the user with a flexible system to control the PART TYPES and how parts are assigned to a Part
PartBuilder
PartBuilder extracts pin-data for electronic components from a wide variety of sources and creates schematic symbol files used by popular industry EDA tools including: Cadence Allegro-HDL Cadence Orcad Capture and Orcad Capture CIS Mentor dxDesigner and
PartBuilder Programmable Logic Symbol Flows
CadEnhance defines 2 different flows (Physical and Logical) for FPGA and CPLD symbol creation. Figure 6 below shows the I/O structure of a typical modern FPGA/CPLD which is built as a collection of general purpose I/O banks and specialty HIGH speed I/O ba
PartBuilder Slides Shows
@self Links to Download Slide Shows Right click on link and select "save link as..." to Download PartBuilder Overview Summary Slides Its best to watch this as a slide show (Because the animation helps to convey concepts) after downloading you can
PartList (BOM) Comparison Reports
The BOM Compare identifies changes in parts and part properties between the two designs. Note that NetBom considers the value of the selected BOM_IGNORE property described in the Configuration Variables http://www.cadenhance.com/Documentation/NetBom/Confi
PIN_GROUP_ASSIGN_FILE
PIN_GROUP_TO_SYMBOL_MAP (PGSM) File PIN_NUM_TYPE FILE The PIN_NUM_TYPE File is hand built in a text editor or Spreadsheet Program. It does not describe the layout of the symbols, it only provides the pin_name, pin_number, pin_type and optionally the IO Standard of each pin . The PIN_NUM_TYPE file starts with
PIN_TYPE_OVRD File
The PIN_TYPE_OVRD file is a text file that contains mappings of PIN_NAME matches to PIN_TYPES Any line starting with a '#' is a comment PartBuilder creates a list from this file of all PIN_MATCHES. It then sorts the PIN_MATCHES by length and applies the
PinData Verification Checks
Missing Pin Checks Starting after v18.11.1 PartBuilder has improved facilities to describe the expected pins in a device. The combination of the PCHK_DEVICE_PIN_NUMBERS Entry and the PCHK_VALID_MISSING_PINS Entry allow the user to easily define a very com
PINOUT_TEMPLATE Files
The PINOUT_TEMPLATE file is one of the simplest file to generate to describe the component pin information and the desired symbol layout at the same time (This is the one flow that does not require a symbolOrder.txt file) The file is built manually by the
PinWire Config Files
Important Concepts when using PinWire Config Files The settings displayed in the pinWire GUI The PinWire Gui are what will be used to control how wires are named and terminated when the user hits the run button and selects the pins to wire. The settings c
PROP_LOC_CTL_FILE
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QQuick Look at the DataSheetWe Look at the ball assignments and pinout diagram in the DataSheet We are interested in the 96 Ball x16 device Functional Diagram The Functional Diagrm shows us the Address and Control Pins on the left and the Data Pins, Strobes and Data Mask pins on the
Quick Look at the SDL-EDITOR Operations
The SDL-Editor makes it easy to: Create/Remove symbols, Move pinMatches within or between symbols, insert grid spaces between pin Control the sides the pinMatch will be placed on Add special modifiers like bubbles/clocks and dpairs to the symbols Here i
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RRead Pin Report for the first time1. Read the PIN_REPORT File for the first time click the Read Pin Report Button on the Extra Config Options Menu (or double click the READ_PIN_REPORT Tree Item in the center of the Main Gui PartBuilder has many ways to start the same operation image2019-1
READ_PIN_REPORT
image2018-10-31_17-2-41.png READ_PIN_REPORT The READ_PIN_REPORT goes through several steps: image2018-10-31_17-3-37.png Read and Verify Pin Report File The First step is to read the Selected PIN_REPORT_FILE. The PIN_REPORT_TYPE setting tells PartBuilder w
Reference Information for dal constraint tool
@self dal Constraints/Stackup PowerPoint Its best to right click on this link and save it locally. Then use the presentation mode because some of the animation helps explain the concepts. Sample CRF File This is a sample Constraint Rules File spreadshe
Regroup the DataPins and Move to Bottom of ALL_SIGNAL_PINS symbol.
Here we are going to organize the pins the way we want them to appear on the symbols. For the first pass we will keep the 2 symbols ALL_SIGNAL_PINS and POWER_PINS_1 It may be helpful to refer back to Tutorial 1. DDR3 DRAM From IBIS Model page to see what
Regular Expression Rename Rules DiffPair Renaming... Example 1
The Rename Rules use the full power of the Perl Regular expression engine to perform search and replace on the pin_names. The following example describes a powerful set of regular expression used to rename some strangely named clk output pins found in a
Regular Expressions In CadEnhance Tools
Many of the CadEnhance Tools require the user to enter Regular Expressions as pattern matches for strings or filenames. For example, PartBuilder uses them for multiple purposes including: Matching pins in the SYMBOL_DESCRIPTION_LANGUAGE, Renaming signals
Remap PIN_TYPE and PIN_GROUPS using Pin Explorer
1. Change the pin_match filter to search for VREF,ZQ 2. View the pins we can see that VREFDQ and VREFCA were identified as POWER pins and ZQ was identified as a NC pin... We want VREFDQ and VREFCA to be input pins and ZQ to be an Analog pin 3. we select
Reorganize Address Clock and Control Pins
This video shows how we use cut/paste and move operations to move the address and control pins around to make a well organized section of pins. ReOrganize Address and Control Pins.mp4 The Address, Clock and Control pins are all on the left side of the sym
Request Demo License
This Page Table of Contents Use one of the Installed Tools to request your license CadEnhance will provide a free Demo License to let you work with all of the tools for a 30-day period, and if you need more time to make a decision we will be happy to exte
Run Smart-Frac to create initial SDL File
1. Double Click the SMART-FRAC Entry Note the SYMBOL_DESCRIPTION_FILE entry is empty In this case, SMART-Frac creates the initial Symbol Description Language (SDL) File for us. It identifies and collapses all the busses and diff_pairs in the pinData. It
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SSample CadEnhance License File######################################################################## # TERMS AND CONDITIONS ######################################################################## # # Please read these terms carefully prior to downloading or using the # products. Yo
Saving Your Changes
1. Use the save Changes button on the Main Gui We should do this early and often as we make our changes The settings that we changed get written to the symGenCtl.txt file in the local working directory 2. We take a quick look at the Config Menu 3. Here we
SDL PreProcessor commands
SDL PreProcessor command consist of, the `Include command, the `EXIT statement LOOP_DIRECTIVES and VARIABLE SUBSTITUTION commands. They greatly increase the efficiency of creating parts that contain multiple similar interfaces like a microprocessor with
Searching for Configuration Settings
Searching For Configuration Settings (CSETS) Each CadEnhance tool provides a powerful search function to let users find a CSET by name, value or category. From there they can inspect and/or modify its current value, and also see the source of it's current
Select the IBIS_FILE as the PIN_REPORT_FILE
Step 1 Browse to Find the IBIS_MODEL Step 2 Browse to find the IBIS Model we downloaded In this case, the file was in "C:\Users\boleary\Downloads\v91a_1p35_ibis" Step 3 Step 4 Step 5 Step 6 Move Selected file to working Directory PartBuilder saw that the
Sharing your Archive with CadEnhance Support
Once you Archive your working folder you can share it with CadEnhance Support using the Tool Help/Online Problem Reporting Menu Item. image-20230725-105344.png Create a Request for your Issue and attach the archive.zip file to the request.
SIG_RENAME_RULES
There are occasions where the user might want to change the name of a pin we extracted from the PIN_REPORT_FILE. PartBuilder provides a function to rename the pins AFTER extracting the pin-data so that the user does not have to hand edit the PIN_REPORT_FI
Simple example of the Symbol Description Language
An example SDL file to describe a fictitious x16 DRAM Part PartBuilder reads this 35 line SDL file and divides up the pins of this 200 pin DRAM into 5 schematic symbols. The SDL File Is shown on the Left It was created in Excel and saved off as a .csv f
Simple exercise for the User
When we created the parts, we showed what we were going to build, and then we Edited the SDL. Its very likely that the SDL for the ADDRESS_CTL_PINS symbol didn't exactly match what we said we'd create The order of the CAS, RAS...RST pins is probably diff
SIMPLE_BGA Example1 FAKE_DRAM
Download this file to build this part BETTER_FAKE_DRAM.zip The FAKE_DRAM SIMPLE_BGA spreadsheet shows the layout of the pins of the fictional DRAM part built for this example image2017-2-9_8-26-25.png The SIMPLE_BGA PIN_REPORT_FILE is shown above, the PIN
SIMPLE_BGA File
The SIMPLE_BGA File format makes it easy to enter all the pins from a BGA quickly. It is easiest to create this in a spreadsheet program, and the pins can often be copied directly from a pdf. The pin_names are entered into the rows and columns of the BGA,
SIMPLE_TQFP Pin Report
The SIMPLE_TQFP File format makes it easy to enter all the pins from a DataSheet that provides the device pinout using the Layout of the TQFP or inline package pins This report type allows the user to export the pdf pinout from a datasheet into a spreadsh
Smart SIG_NAME(s) Entry
There are many times the names of existing symbol pins do not work well to create an Intelligent signal name for its attached wire For these cases the Smart SIG_NAME(s) Entry is optimized to do the required work for the designer image2018-12-20_14-52-41.p
SMART-FRAC
image2018-10-31_16-59-12.png SMART-FRAC The SMART-FRAC Step analyzes the pinData and creates the Initial SDL Template file to let the user get started organizing the pins into symbols. SMART-FRAC does things a little differently depending on what PIN_REPO
SPREADSHEET PIN_REPORT_TYPES
@self GENERIC_CSV_FILE and SPREADSHEET The SPREADSHEET and GENERIC_CSV_FILE allow the user to provide pinData using a very flexible spreadsheet format The user must provide PartBuilder with extra configuration details to detail the layout of pinData w
Starting CE-HDL from Allegro
Starting CE-HDL from AllegroHDL Once the CE-HDL tools have been installed There are 2 or 3 ways to start the CE-HDL GUI from AllegroHDL. The user can use the menu to select the CE-HDL item which will start the tool The user can also type the CE-HDL (case
Step by Step Symbol Creation
CadEnhance recommends using a separate working directory or folder for each Part you are creating. When PartBuilder is installed, it creates a workdir directory under the root install directory, which is a good place to store part folders, But you can us
Suspicious Nets Report (With Config Info)
This report is governed by the DESIGN_AUDIT_SUSPICIOUS_NET_CONFIG CSet.
Symbol Description Language (SDL)
The CadEnhance Symbol Description Language (SDL) enables the user to describe the layout of pins and symbols at a very high level. It supports looping constructs and pin-name pattern matching which enables features designers haven't seen before in symbol
Symbol Description Language Structure and Syntax
The Structure and Syntax of the CadEnhance Symbol Description Language (SDL) is described here Symbol Description Language Structure The Symbol Description Language (SDL) was designed to be uber-efficient at describing schematic symbol construction, while
SYMBOL_DESCRIPTION_FILE
04-02-2017-09-13-56.png The SYMBOL_DESCRIPTION_FILE holds the Symbol Description Language (SDL) required to describe the symbols which will be generated to represent the part. It can be a plain text file or a comma separated values (csv) file which is e
System Requirements
The CadEnhance Tools Run on a Standard Windows Platform and Newer Linux Platforms. Part Builder builds Symbols for: Cadence Allegro-HDL, Orcad Capture and Capture-CIS, Mentor Graphics DxDesigner and PADs Professional Tools CadSoft Eagle 7.7.0 Software
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TTesting License CheckoutLicense Checkout Test Using the CadEnhance Tools The Tools offer a built-in license test feature which attempts to checkout the appropriate feature from either the node locked license file, or the Flexera License Server It is best to use the 2 environmen
The CE-HDL GUI
The CE_HDL GUI. After starting the CeHDL tool, a GUI will popup, similar to the one shown on the right. In the Windows version, a debug console will also popup. This window can be minimized to keep it out of the way, or it can be disabled following these
The Constraint Rule File (CRF)
The Constraint Rules File (CRF) is a Spreadsheet created by the Design Engineer(s) and is used to specify complex Physical and Electrical Design Constraints for the Allegro PCB Editor. Constraints are specified as high level Macros and use very powerful n
The PartBuilder Symbol Creation Flow
The video above demonstrates the high level view of the PartBuilder schematic symbol creation process. PartBuilder reads the PIN_REPORT_FILE to build an internal pin database, then reads the Symbol Description Language(SDL) file to map the pins to locatio
The PinData to Symbol Creation Pipeline
Follow this link to watch a video detailing the PartBuilder Symbol Creation PipeLine:PartBuilderSymbolCreationPipeLine http://scast.cadenhance.com/PartBuilderSymbolCreationPipeLine image2018-10-31_17-8-2.png This diagram shows all the steps in the Symbol
The PinWire Gui
The PinWire GUI. After double clicking the Pin_Wire tool from the HDL Tool Selection Tree, the PinWire GUI will popup, similar to the one shown on the right. The GUI has 5 main sections: Signal/Pin and Power Rename Rules Signal Naming Options Part Optio
Top Menu Bar
The Menu Bar provides the Config, License Updates and Help Menu items image2019-8-26_14-36-23.png Config Menu image2019-8-26_14-36-54.png View/Set All Config Variables Pops up a GUI to interact with all the available Configuration Settings used by the To
Tutorial 1. DDR3 DRAM From IBIS Model
Follow Along with these Pages to build symbols for the DDR3 DRAM Device The steps in this tutorial were captured on a Windows 10 host using the v19.1.1 Release of the CadEnhance Tools. The look and feel of the screen shots will differ slightly when runn
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UUsing Renaming Rules with CadEnhance ToolsThe CadEnhance Tools support Renaming Rules for many of the opearations performed on Text Strings PartBuilder uses Rename Rules to rename Pins, strip PinNumbers from within PinNames, and remove leading zeros from PinNumbers or PinNames extracted from Pin
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VVew/Set All Configuration SettingsAccessing View/Set All Configuration Settings in NetBom image-20230725-140536.png CONFIG SETTINGS GUI When the user chooses View/Set All Configuration Settings, the CONFIGURATION SETTINGS GUI similar to the one from the NetBom Tool shown to the right will
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WWeb Report FeaturesThe primary product of a NetBom operation is a collection of Web Reports that be viewed in any browser (though Chrome/Edge is recommended). These web reports share many features, and most of the reports are present in every operation. Further documentatio
Windows Installation using self extracting .exe file
This Page Table of Contents This Page Tree @self Latest Windows Installation Video Video of Latest Windows Installation Process July 2022 https://scast.cadenhance.com/ce_tools_install_2022 Click on the Windows button to download the CadEnhance tools. Dow
Working with Flexera License Servers
eSupport for floating licenses with the Flexera License Server was added starting with Version 18.9.1 of the CadEnhance Tool Suite. User Inputs The user will be required to provide cadEnhance with the hostid (MAC Address) and hostName of the server they
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XXILINX Package FileVivado Package File (preferred) The Xilinx tool sets provide commands to generate their "package file" which contains the ascii description of all the pins in their part. In their ISE tool for parts up to the Virtex6 family, they provided a "partGen" comm
Xilinx Pad File
The Xilinx Pad File is the report generated after the FPGA design is compiled. It contains most of the information in the package file, but it adds more information about the way the pin gets used in the design, including the pin functional name, the IO S
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